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| Presentation | 2005-01-18 15:15 A 10-Gbit/s CMOS burst-mode clock and data recovery IC for high-speed access networks Shunji Kimura, Masafumi Nogawa, Kazuyoshi Nishimura, Tomoaki Yoshida, Kiyomi Kumozaki, Susumu Nishihara, Yusuke Ohtomo (NTT) Link to ES Tech. Rep. Archives:  ED2004-223 MW2004-230 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We fabricated a 10-Gbit/s burst-mode clock and data recovery IC with a CMOS process for future high-speed access networks. Key technologies of our circuit are an input buffer amplifier that offers capacitive coupling at the input port and a new bit gating circuit that improves the duty-cycle variation tolerance of the clock recovery circuit. Our fabricated IC test board achieved error-free operations for the continuous and the asynchronous-packet signals. In the burst mode, the measured number of minimum preamble bits was less than 16 and the receivable duty-cycle variation range was 44 to over 59%. A power consumption was 1.2 W. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Burst-mode transmission / Clock and data recovery circuit / Instantaneous phase synchronization circuit / Gated oscillator / Gating circuit / Capacitive coupling / Input buffer amplifier / Access network | |
| Reference Info. | IEICE Tech. Rep., vol. 104, no. 552, MW2004-230, pp. 65-70, Jan. 2005. | |
| Paper # | MW2004-230 | |
| Date of Issue | 2005-01-11 (ED, MW) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ED2004-223 MW2004-230 |
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| Conference Information | |
| Committee | MW ED |
| Conference Date | 2005-01-17 - 2005-01-18 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | MW |
| Conference Code | 2005-01-MW-ED |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 10-Gbit/s CMOS burst-mode clock and data recovery IC for high-speed access networks |
| Sub Title (in English) | |
| Keyword(1) | Burst-mode transmission |
| Keyword(2) | Clock and data recovery circuit |
| Keyword(3) | Instantaneous phase synchronization circuit |
| Keyword(4) | Gated oscillator |
| Keyword(5) | Gating circuit |
| Keyword(6) | Capacitive coupling |
| Keyword(7) | Input buffer amplifier |
| Keyword(8) | Access network |
| 1st Author's Name | Shunji Kimura |
| 1st Author's Affiliation | NTT Corporation (NTT) |
| 2nd Author's Name | Masafumi Nogawa |
| 2nd Author's Affiliation | NTT Corporation (NTT) |
| 3rd Author's Name | Kazuyoshi Nishimura |
| 3rd Author's Affiliation | NTT Corporation (NTT) |
| 4th Author's Name | Tomoaki Yoshida |
| 4th Author's Affiliation | NTT Corporation (NTT) |
| 5th Author's Name | Kiyomi Kumozaki |
| 5th Author's Affiliation | NTT Corporation (NTT) |
| 6th Author's Name | Susumu Nishihara |
| 6th Author's Affiliation | NTT Corporation (NTT) |
| 7th Author's Name | Yusuke Ohtomo |
| 7th Author's Affiliation | NTT Corporation (NTT) |
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| Speaker | Author-1 |
| Date Time | 2005-01-18 15:15:00 |
| Presentation Time | 25 minutes |
| Registration for | MW |
| Paper # | ED2004-223, MW2004-230 |
| Volume (vol) | vol.104 |
| Number (no) | no.550(ED), no.552(MW) |
| Page | pp.65-70 |
| #Pages | 6 |
| Date of Issue | 2005-01-11 (ED, MW) |
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