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Paper Abstract and Keywords
Presentation 2005-01-25 10:30
A variable clock mechanism for Dynamically Reconfigurable Processors
Hideharu Amano, Yoshinori Adachi, Satoshi Tsutsumi, Kenichiro Ishikawa (Keio Univ.)
Abstract (in Japanese) (See Japanese page) 
(in English) (Not available yet)
Keyword (in Japanese) (See Japanese page) 
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Reference Info. IEICE Tech. Rep., vol. 104, no. 591, CPSY2004-65, pp. 13-16, Jan. 2005.
Paper # CPSY2004-65 
Date of Issue 2005-01-18 (VLD, CPSY) 
ISSN Print edition: ISSN 0913-5685
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Conference Information
Committee CPSY VLD IPSJ-SLDM  
Conference Date 2005-01-25 - 2005-01-26 
Place (in Japanese) (See Japanese page) 
Place (in English)  
Topics (in Japanese) (See Japanese page) 
Topics (in English) FPGA and its Application, etc 
Paper Information
Registration To CPSY 
Conference Code 2005-01-CPSY-VLD-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A variable clock mechanism for Dynamically Reconfigurable Processors 
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1st Author's Name Hideharu Amano  
1st Author's Affiliation Keio University (Keio Univ.)
2nd Author's Name Yoshinori Adachi  
2nd Author's Affiliation Keio University (Keio Univ.)
3rd Author's Name Satoshi Tsutsumi  
3rd Author's Affiliation Keio University (Keio Univ.)
4th Author's Name Kenichiro Ishikawa  
4th Author's Affiliation Keio University (Keio Univ.)
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Date Time 2005-01-25 10:30:00 
Presentation Time 30 minutes 
Registration for CPSY 
Paper # VLD2004-99, CPSY2004-65 
Volume (vol) vol.104 
Number (no) no.589(VLD), no.591(CPSY) 
Page pp.13-16 
#Pages
Date of Issue 2005-01-18 (VLD, CPSY) 


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