| Paper Abstract and Keywords |
| Presentation |
2005-01-25 09:30
A Reconfigurable Processor based on ALU array architecture with limitation on the interconnection
Makoto Okada, Tatsuo Hiramatsu, Hiroshi Nakajima, Makoto Ozone, Katsunori Hirase (SANYO Electric), Shinji Kimura (Waseda Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Dynamic reconfigurable processor based on ALU array architecture for consumer appliances is introduced. We propose the ALU array architecture with the limitation on the interconnection for area reduction. With the proposed architecture, we can reduce gate size by 63% on interconnections. In addition, we show that the performance of the proposed architecture is almost the same as one without limitations. The proposed processor is a parallel processing processor that consists of a sequencer and an ALU array, adopted multi threading technology. We develop compilation tools from source codes written in C language for the proposed processor. We demonstrate the software model of the processor using MPEG-4 video decoding application. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Reconfigurable Processor / ALU array / Data Flow Graph / / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 104, no. 591, CPSY2004-63, pp. 1-6, Jan. 2005. |
| Paper # |
CPSY2004-63 |
| Date of Issue |
2005-01-18 (VLD, CPSY) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
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| Conference Information |
| Committee |
CPSY VLD IPSJ-SLDM |
| Conference Date |
2005-01-25 - 2005-01-26 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
|
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
FPGA and its Application, etc |
| Paper Information |
| Registration To |
CPSY |
| Conference Code |
2005-01-CPSY-VLD-IPSJ-SLDM |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
A Reconfigurable Processor based on ALU array architecture with limitation on the interconnection |
| Sub Title (in English) |
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| Keyword(1) |
Reconfigurable Processor |
| Keyword(2) |
ALU array |
| Keyword(3) |
Data Flow Graph |
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| 1st Author's Name |
Makoto Okada |
| 1st Author's Affiliation |
SANYO Electric Co., Ltd. (SANYO Electric) |
| 2nd Author's Name |
Tatsuo Hiramatsu |
| 2nd Author's Affiliation |
SANYO Electric Co., Ltd. (SANYO Electric) |
| 3rd Author's Name |
Hiroshi Nakajima |
| 3rd Author's Affiliation |
SANYO Electric Co., Ltd. (SANYO Electric) |
| 4th Author's Name |
Makoto Ozone |
| 4th Author's Affiliation |
SANYO Electric Co., Ltd. (SANYO Electric) |
| 5th Author's Name |
Katsunori Hirase |
| 5th Author's Affiliation |
SANYO Electric Co., Ltd. (SANYO Electric) |
| 6th Author's Name |
Shinji Kimura |
| 6th Author's Affiliation |
Waseda University (Waseda Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2005-01-25 09:30:00 |
| Presentation Time |
30 minutes |
| Registration for |
CPSY |
| Paper # |
VLD2004-97, CPSY2004-63 |
| Volume (vol) |
vol.104 |
| Number (no) |
no.589(VLD), no.591(CPSY) |
| Page |
pp.1-6 |
| #Pages |
6 |
| Date of Issue |
2005-01-18 (VLD, CPSY) |
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