Paper Abstract and Keywords |
Presentation |
2005-01-25 13:30
[Invited Talk]
* Masanori Imai (STARC) |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Growing complexity of SoC’s and reducing life cycle time of electronic products both are demanding higher design productivity. IP reuse is an absolute must for its solution. Consequently, the growing number of IP cores tend to be integrated into a single chip to improve the productivity. As well known, integrated IP cores include 3rd party IP cores besides dedicated IP ones. The 3rd party IP cores are sometimes said to be problematic in functional quality, which is one of the main roadblocks that disturb IP reuse promotion. Therefore, to ease IP reuse, we need to close design-verification gap in advance by IP quality enhancements and efficient verification methodologies like as the assertion technology. We are developing IP related standards leading to attaining our goals. A guideline for verification IP’s including assertion checkers is one of such standards. Those activities in STARC are outlined. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
assertion / verification / verification IP / testbench / IP / deliverables / HVL / IP quality |
Reference Info. |
IEICE Tech. Rep., vol. 104, no. 589, VLD2004-103, pp. 35-38, Jan. 2005. |
Paper # |
VLD2004-103 |
Date of Issue |
2005-01-18 (VLD, CPSY) |
ISSN |
Print edition: ISSN 0913-5685 |
Download PDF |
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Conference Information |
Committee |
CPSY VLD IPSJ-SLDM |
Conference Date |
2005-01-25 - 2005-01-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA and its Application, etc |
Paper Information |
Registration To |
VLD |
Conference Code |
2005-01-CPSY-VLD-IPSJ-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
* |
Sub Title (in English) |
* |
Keyword(1) |
assertion |
Keyword(2) |
verification |
Keyword(3) |
verification IP |
Keyword(4) |
testbench |
Keyword(5) |
IP |
Keyword(6) |
deliverables |
Keyword(7) |
HVL |
Keyword(8) |
IP quality |
1st Author's Name |
Masanori Imai |
1st Author's Affiliation |
Semiconductor Technology Academic Research Center (STARC) |
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Speaker |
Author-1 |
Date Time |
2005-01-25 13:30:00 |
Presentation Time |
30 minutes |
Registration for |
VLD |
Paper # |
VLD2004-103, CPSY2004-69 |
Volume (vol) |
vol.104 |
Number (no) |
no.589(VLD), no.591(CPSY) |
Page |
pp.35-38 |
#Pages |
4 |
Date of Issue |
2005-01-18 (VLD, CPSY) |
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