| Paper Abstract and Keywords |
| Presentation |
2005-01-26 14:40
ASIP Architecture for Real-Time Graphical Effect Acceleration
Tatsuhiro Yoshimura, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Graphical effect processing realizes a variety of
visual representation.
In this paper, we propose an ASIP architecture for
real-time graphical effect processing.
The proposed architecutre consists of ASIP(Application Specific Instruction
set Processor)and memory access unit specified for graphical effect
processing.
We implemented an ASIP based on the proposed architecture,
and evaluated execution time of graphical
effects processing on instruction set simulator(ISS).
Results of logic synthesis and evaluation on ISS show
that the proposed architecture can process real-time
graphical effects with additional small H/W cost.
\end{eabstract} |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
digital image processing / graphical effect / ASIP / memory access circuit / / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 104, no. 590, VLD2004-118, pp. 49-54, Jan. 2005. |
| Paper # |
VLD2004-118 |
| Date of Issue |
2005-01-19 (VLD, CPSY) |
| ISSN |
Print edition: ISSN 0913-5685 |
| Download PDF |
|
| Conference Information |
| Committee |
CPSY VLD IPSJ-SLDM |
| Conference Date |
2005-01-25 - 2005-01-26 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
|
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
FPGA and its Application, etc |
| Paper Information |
| Registration To |
VLD |
| Conference Code |
2005-01-CPSY-VLD-IPSJ-SLDM |
| Language |
Japanese |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
ASIP Architecture for Real-Time Graphical Effect Acceleration |
| Sub Title (in English) |
|
| Keyword(1) |
digital image processing |
| Keyword(2) |
graphical effect |
| Keyword(3) |
ASIP |
| Keyword(4) |
memory access circuit |
| Keyword(5) |
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| Keyword(6) |
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| 1st Author's Name |
Tatsuhiro Yoshimura |
| 1st Author's Affiliation |
Osaka University (Osaka Univ.) |
| 2nd Author's Name |
Keishi Sakanushi |
| 2nd Author's Affiliation |
Osaka University (Osaka Univ.) |
| 3rd Author's Name |
Yoshinori Takeuchi |
| 3rd Author's Affiliation |
Osaka University (Osaka Univ.) |
| 4th Author's Name |
Masaharu Imai |
| 4th Author's Affiliation |
Osaka University (Osaka Univ.) |
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| Speaker |
Author-1 |
| Date Time |
2005-01-26 14:40:00 |
| Presentation Time |
30 minutes |
| Registration for |
VLD |
| Paper # |
VLD2004-118, CPSY2004-84 |
| Volume (vol) |
vol.104 |
| Number (no) |
no.590(VLD), no.592(CPSY) |
| Page |
pp.49-54 |
| #Pages |
6 |
| Date of Issue |
2005-01-19 (VLD, CPSY) |