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| Presentation | 2005-04-14 09:30 Low-Power Embedded SRAM Modules with Expanded Margins for Writing Masanao Yamaoka (Hitachi, Ltd.), Noriaki Maeda (Renesas), Yoshihiro Shinozaki (Hitachi ULSI), Yasuhisa Shimazaki, Koji Nii, Shigeru Shimada, Kazumasa Yanagisawa (Renesas), Takayuki Kawahara (Hitachi, Ltd.) Link to ES Tech. Rep. Archives:  ICD2005-2 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The power consumption of a low-power SoC has a battery life of mobile appliances. The general SoCs have large on-chip SRAMs, which consume a large proportion of whole LSI power. For realizing a low-power SoC, we have developed embedded SRAM modules, which use writing margin expanding technique, rocess variation adaptive writing replica circuit and reducing leakage current technique. These low-power techniques enable the SRAM modules to achieve low active and low standby power consumption. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Low-power SRAM / Low-power SoC / write margin / low-leakage word-line driver / replica circuit / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 1, ICD2005-2, pp. 7-12, April 2005. | |
| Paper # | ICD2005-2 | |
| Date of Issue | 2005-04-07 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2005-2 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2005-04-14 - 2005-04-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2005-04-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Low-Power Embedded SRAM Modules with Expanded Margins for Writing |
| Sub Title (in English) | |
| Keyword(1) | Low-power SRAM |
| Keyword(2) | Low-power SoC |
| Keyword(3) | write margin |
| Keyword(4) | low-leakage word-line driver |
| Keyword(5) | replica circuit |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Masanao Yamaoka |
| 1st Author's Affiliation | Hitachi, Ltd. (Hitachi, Ltd.) |
| 2nd Author's Name | Noriaki Maeda |
| 2nd Author's Affiliation | Renesas Technology Corp. (Renesas) |
| 3rd Author's Name | Yoshihiro Shinozaki |
| 3rd Author's Affiliation | Hitachi ULSI Systems (Hitachi ULSI) |
| 4th Author's Name | Yasuhisa Shimazaki |
| 4th Author's Affiliation | Renesas Technology Corp. (Renesas) |
| 5th Author's Name | Koji Nii |
| 5th Author's Affiliation | Renesas Technology Corp. (Renesas) |
| 6th Author's Name | Shigeru Shimada |
| 6th Author's Affiliation | Renesas Technology Corp. (Renesas) |
| 7th Author's Name | Kazumasa Yanagisawa |
| 7th Author's Affiliation | Renesas Technology Corp. (Renesas) |
| 8th Author's Name | Takayuki Kawahara |
| 8th Author's Affiliation | Hitachi, Ltd. (Hitachi, Ltd.) |
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| Speaker | Author-1 |
| Date Time | 2005-04-14 09:30:00 |
| Presentation Time | 30 minutes |
| Registration for | ICD |
| Paper # | ICD2005-2 |
| Volume (vol) | vol.105 |
| Number (no) | no.1 |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2005-04-07 (ICD) |
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