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| Presentation | 2005-04-14 11:40 A 128Mb DRAM Using a 1T Gain Cell(FBC) on SOI Takashi Ohsawa, Katsuyuki Fujita, Kosuke Hatsuda (Toshiba), Tomoki Higashi (Toshiba Microelectronics), Mutsuo Morikado, Yoshihiro Minami, Tomoaki Shino, Hiroomi Nakajima, Kazumi Inoh, Takeshi Hamamoto, Shigeyoshi Watanabe (Toshiba) Link to ES Tech. Rep. Archives:  ICD2005-5 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We report on a 128Mbit DRAM design using the capacitor-less DRAM cell or the floating body cell(FBC) on SOI. The cell of data “1” is necessary to be restored after read due to charge pumping. It is also important to reduce the refresh busy rate. We place a sense amplifier per bit line in order to fulfill those requirements and operate them asymmetrically between a minority number of selected ones and a majority number of unselected ones, leading to about 50% power reduction on the average compared with the conventional symmetrical operation. A dummy cell system where 128 “1” cells and 128 “0” cells are read and are averaged is shown to be very useful to obtain a very accurate reference current source to distinguish the data “1” and “0”, since the system reduces its dispersion drastically. We show that 18.5ns random access time is simulated with all cells in the 128Mb DRAM functional having a reasonable amount of redundancy. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | SOI / Capacitor-less DRAM / FBC / Gain Cell / Embedded Memory / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 1, ICD2005-5, pp. 23-28, April 2005. | |
| Paper # | ICD2005-5 | |
| Date of Issue | 2005-04-07 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2005-5 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2005-04-14 - 2005-04-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2005-04-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 128Mb DRAM Using a 1T Gain Cell(FBC) on SOI |
| Sub Title (in English) | |
| Keyword(1) | SOI |
| Keyword(2) | Capacitor-less DRAM |
| Keyword(3) | FBC |
| Keyword(4) | Gain Cell |
| Keyword(5) | Embedded Memory |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Takashi Ohsawa |
| 1st Author's Affiliation | Toshiba Corporation Semiconductor Company (Toshiba) |
| 2nd Author's Name | Katsuyuki Fujita |
| 2nd Author's Affiliation | Toshiba Corporation Semiconductor Company (Toshiba) |
| 3rd Author's Name | Kosuke Hatsuda |
| 3rd Author's Affiliation | Toshiba Corporation Semiconductor Company (Toshiba) |
| 4th Author's Name | Tomoki Higashi |
| 4th Author's Affiliation | Toshiba Microelectronics Corporation (Toshiba Microelectronics) |
| 5th Author's Name | Mutsuo Morikado |
| 5th Author's Affiliation | Toshiba Corporation Semiconductor Company (Toshiba) |
| 6th Author's Name | Yoshihiro Minami |
| 6th Author's Affiliation | Toshiba Corporation Semiconductor Company (Toshiba) |
| 7th Author's Name | Tomoaki Shino |
| 7th Author's Affiliation | Toshiba Corporation Semiconductor Company (Toshiba) |
| 8th Author's Name | Hiroomi Nakajima |
| 8th Author's Affiliation | Toshiba Corporation Semiconductor Company (Toshiba) |
| 9th Author's Name | Kazumi Inoh |
| 9th Author's Affiliation | Toshiba Corporation Semiconductor Company (Toshiba) |
| 10th Author's Name | Takeshi Hamamoto |
| 10th Author's Affiliation | Toshiba Corporation Semiconductor Company (Toshiba) |
| 11th Author's Name | Shigeyoshi Watanabe |
| 11th Author's Affiliation | Toshiba Corporation Semiconductor Company (Toshiba) |
| 12th Author's Name | |
| 12th Author's Affiliation | () |
| 13th Author's Name | |
| 13th Author's Affiliation | () |
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| 14th Author's Affiliation | () |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2005-04-14 11:40:00 |
| Presentation Time | 30 minutes |
| Registration for | ICD |
| Paper # | ICD2005-5 |
| Volume (vol) | vol.105 |
| Number (no) | no.1 |
| Page | pp.23-28 |
| #Pages | 6 |
| Date of Issue | 2005-04-07 (ICD) |
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