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| Presentation | 2005-04-15 10:30 A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture Takaharu Tsuji (Renesas Technorogy), Hiroaki Tanizaki (Renesas Device Design), Masatoshi Ishikawa, Jun Otani, Yuichiro Yamaguchi, Shuichi Ueno, Tsukasa Oishi, Hideto Hidaka (Renesas Technorogy) Link to ES Tech. Rep. Archives:  ICD2005-13 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A 1Mbit MRAM with a 0.81um2 1-Transistor 1-Magnetic Tunnel Junction (1T-1MTJ) cell using 0.13um 4LM logic technology has been produced. A folded-bitline sensing and common write word-line scheme with dummy row architecture achieves 100MHz random read cycle with n+ diffusion/Co-saliside read source lines. Employing a distributed gate voltage control scheme, high speed write current switching without write disturb by peak current even at 1.2V power supply is demonstrated. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | MRAM / Magnetoresistive random access memory / nonvolatile / embedded / low voltage / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 2, ICD2005-13, pp. 1-6, April 2005. | |
| Paper # | ICD2005-13 | |
| Date of Issue | 2005-04-08 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2005-13 |
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| Conference Information | |
| Committee | ICD |
| Conference Date | 2005-04-14 - 2005-04-15 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2005-04-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture |
| Sub Title (in English) | |
| Keyword(1) | MRAM |
| Keyword(2) | Magnetoresistive random access memory |
| Keyword(3) | nonvolatile |
| Keyword(4) | embedded |
| Keyword(5) | low voltage |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Takaharu Tsuji |
| 1st Author's Affiliation | Renesas Technorogy Corporation (Renesas Technorogy) |
| 2nd Author's Name | Hiroaki Tanizaki |
| 2nd Author's Affiliation | Renesas Device Design Corporation (Renesas Device Design) |
| 3rd Author's Name | Masatoshi Ishikawa |
| 3rd Author's Affiliation | Renesas Technorogy Corporation (Renesas Technorogy) |
| 4th Author's Name | Jun Otani |
| 4th Author's Affiliation | Renesas Technorogy Corporation (Renesas Technorogy) |
| 5th Author's Name | Yuichiro Yamaguchi |
| 5th Author's Affiliation | Renesas Technorogy Corporation (Renesas Technorogy) |
| 6th Author's Name | Shuichi Ueno |
| 6th Author's Affiliation | Renesas Technorogy Corporation (Renesas Technorogy) |
| 7th Author's Name | Tsukasa Oishi |
| 7th Author's Affiliation | Renesas Technorogy Corporation (Renesas Technorogy) |
| 8th Author's Name | Hideto Hidaka |
| 8th Author's Affiliation | Renesas Technorogy Corporation (Renesas Technorogy) |
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| Speaker | Author-1 |
| Date Time | 2005-04-15 10:30:00 |
| Presentation Time | 30 minutes |
| Registration for | ICD |
| Paper # | ICD2005-13 |
| Volume (vol) | vol.105 |
| Number (no) | no.2 |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2005-04-08 (ICD) |
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