Paper Abstract and Keywords |
Presentation |
2005-04-15 10:30
A 1.2V 1Mbit Embedded MRAM Core with Folded Bit-Line Array Architecture Takaharu Tsuji (Renesas Technorogy), Hiroaki Tanizaki (Renesas Device Design), Masatoshi Ishikawa, Jun Otani, Yuichiro Yamaguchi, Shuichi Ueno, Tsukasa Oishi, Hideto Hidaka (Renesas Technorogy) Link to ES Tech. Rep. Archives: ICD2005-13 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
A 1Mbit MRAM with a 0.81um2 1-Transistor 1-Magnetic Tunnel Junction (1T-1MTJ) cell using 0.13um 4LM logic technology has been produced. A folded-bitline sensing and common write word-line scheme with dummy row architecture achieves 100MHz random read cycle with n+ diffusion/Co-saliside read source lines. Employing a distributed gate voltage control scheme, high speed write current switching without write disturb by peak current even at 1.2V power supply is demonstrated. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
MRAM / Magnetoresistive random access memory / nonvolatile / embedded / low voltage / / / |
Reference Info. |
IEICE Tech. Rep., vol. 105, no. 2, ICD2005-13, pp. 1-6, April 2005. |
Paper # |
ICD2005-13 |
Date of Issue |
2005-04-08 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
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Link to ES Tech. Rep. Archives: ICD2005-13 |