Paper Abstract and Keywords |
Presentation |
2005-10-20 15:30
A Memory Controller that Reduces Latency of Cached SDRAM Seiji Miura, Satoru Akiyama (Hitachi,Ltd) Link to ES Tech. Rep. Archives: ICD2005-129 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
The proposed controller has two main control schemes, address-alignment control and dummy-cache control scheme. These two schemes cooperatively control cached SDRAM to reduce its latency. Testing of the controller using benchmark programs demonstrated that latency was reduced 25% and execution time was reduced 13% compare to those of a sense-amplifier cache controller for standard SDRAM. The proposed controller requires 9.3Kgates at a supply voltage of 1.8V and an operating frequency of 133MHz. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
cached SDRAM / memory controller / latency / dummy-cache control scheme / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 105, no. 351, ICD2005-129, pp. 89-93, Oct. 2005. |
Paper # |
ICD2005-129 |
Date of Issue |
2005-10-13 (SIP, ICD, IE) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
Link to ES Tech. Rep. Archives: ICD2005-129 |
Conference Information |
Committee |
SIP ICD IE IPSJ-SLDM |
Conference Date |
2005-10-20 - 2005-10-21 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Ichinobo, Sakunami-Spa |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Processor, DSP, Image Engineering and etc. |
Paper Information |
Registration To |
ICD |
Conference Code |
2005-10-SIP-ICD-IE-IPSJ-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Memory Controller that Reduces Latency of Cached SDRAM |
Sub Title (in English) |
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cached SDRAM |
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memory controller |
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latency |
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dummy-cache control scheme |
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1st Author's Name |
Seiji Miura |
1st Author's Affiliation |
Hitachi,Ltd (Hitachi,Ltd) |
2nd Author's Name |
Satoru Akiyama |
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Hitachi,Ltd (Hitachi,Ltd) |
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Speaker |
Author-1 |
Date Time |
2005-10-20 15:30:00 |
Presentation Time |
20 minutes |
Registration for |
ICD |
Paper # |
SIP2005-110, ICD2005-129, IE2005-74 |
Volume (vol) |
vol.105 |
Number (no) |
no.349(SIP), no.351(ICD), no.353(IE) |
Page |
pp.89-93 |
#Pages |
5 |
Date of Issue |
2005-10-13 (SIP, ICD, IE) |
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