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| Paper Abstract and Keywords | ||
| Presentation | 2005-10-21 10:50 Compaction of Arithmetic Unit with Bit-Level-Parallelism Jubee Tada (Yamagata Univ.), Ryusuke Egawa (Tohoku Univ.), Gensuke Goto (Yamagata Univ.), Tadao Nakamura (Tohoku Univ.) Link to ES Tech. Rep. Archives:  ICD2005-139 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Aiming at reducing power consumption of VLSIs, we propose a fast and compact arithmetic unit. The arithmetic unit reduces static power consumption by the compaction or the circuit scale. To realize that compaction of the arithmetic unit, we exploit bit level parallelism of arithmetic operation, and also, our approach keeps the throughput and saves a dynamic power consumption employing advanced pipelining technique. The simulation results show a high validity of our proposal on VLSI design in deep submicron era. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Low-power / Arithmetic Unit / Wave-Pipelining / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 352, ICD2005-139, pp. 31-35, Oct. 2005. | |
| Paper # | ICD2005-139 | |
| Date of Issue | 2005-10-14 (SIP, ICD, IE) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2005-139 |
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| Conference Information | |
| Committee | SIP ICD IE IPSJ-SLDM |
| Conference Date | 2005-10-20 - 2005-10-21 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ichinobo, Sakunami-Spa |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Processor, DSP, Image Engineering and etc. |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2005-10-SIP-ICD-IE-IPSJ-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Compaction of Arithmetic Unit with Bit-Level-Parallelism |
| Sub Title (in English) | |
| Keyword(1) | Low-power |
| Keyword(2) | Arithmetic Unit |
| Keyword(3) | Wave-Pipelining |
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| 1st Author's Name | Jubee Tada |
| 1st Author's Affiliation | Yamagata University (Yamagata Univ.) |
| 2nd Author's Name | Ryusuke Egawa |
| 2nd Author's Affiliation | Tohoku University (Tohoku Univ.) |
| 3rd Author's Name | Gensuke Goto |
| 3rd Author's Affiliation | Yamagata University (Yamagata Univ.) |
| 4th Author's Name | Tadao Nakamura |
| 4th Author's Affiliation | Tohoku University (Tohoku Univ.) |
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| Speaker | Author-1 |
| Date Time | 2005-10-21 10:50:00 |
| Presentation Time | 20 minutes |
| Registration for | ICD |
| Paper # | SIP2005-120, ICD2005-139, IE2005-84 |
| Volume (vol) | vol.105 |
| Number (no) | no.350(SIP), no.352(ICD), no.354(IE) |
| Page | pp.31-35 |
| #Pages | 5 |
| Date of Issue | 2005-10-14 (SIP, ICD, IE) |
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