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Paper Abstract and Keywords
Presentation 2005-10-21 14:40
A Cache-Defect-Aware Code Placement Technique for Improving the Performance of Processor
Tohru Ishihara (Kyushu Univ.), Farzan Fallah (FLA) Link to ES Tech. Rep. Archives: ICD2005-144
Abstract (in Japanese) (See Japanese page) 
(in English) (Not available yet)
Keyword (in Japanese) (See Japanese page) 
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Reference Info. IEICE Tech. Rep., vol. 105, pp. 61-66, Oct. 2005.
Paper #  
Date of Issue 2005-10-14 (SIP, ICD, IE) 
ISSN Print edition: ISSN 0913-5685
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee SIP ICD IE IPSJ-SLDM  
Conference Date 2005-10-20 - 2005-10-21 
Place (in Japanese) (See Japanese page) 
Place (in English) Ichinobo, Sakunami-Spa 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Processor, DSP, Image Engineering and etc. 
Paper Information
Registration To IPSJ-SLDM 
Conference Code 2005-10-SIP-ICD-IE-IPSJ-SLDM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Cache-Defect-Aware Code Placement Technique for Improving the Performance of Processor 
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1st Author's Name Tohru Ishihara  
1st Author's Affiliation Kyushu University (Kyushu Univ.)
2nd Author's Name Farzan Fallah  
2nd Author's Affiliation Fujitsu Laboratories of America (FLA)
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Date Time 2005-10-21 14:40:00 
Presentation Time 20 minutes 
Registration for IPSJ-SLDM 
Paper # SIP2005-125, ICD2005-144, IE2005-89 
Volume (vol) vol.105 
Number (no) no.350(SIP), no.352(ICD), no.354(IE) 
Page pp.61-66 
#Pages
Date of Issue 2005-10-14 (SIP, ICD, IE) 


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