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| Presentation | 2005-10-21 10:10 Development of an embedded processor core SH-X2 Takashi Okada (Hitachi), Tomoichi Hayashi, Takehiro Shimizu (Renesas), Fumio Arakawa, Tetsuya Yamada (Hitachi), Osamu Nishii, Toshihiro Hattori (Renesas) Link to ES Tech. Rep. Archives:  ICD2005-137 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A {S}uper{H$^{\rm TM}$} embedded processor core, SH-X2 for consumer appliances, implemented in a 90-nm CMOS process running at 800 MHz with a voltage of 1.2V. It has a dual-issue eight-stage pipeline architecture. It archives 1440 MIPS, 5.6GFLOPS and 73M polygons/s at 800MHz. This paper focuses on low-power design method and the implementation of floating-point unit of the SH-X2. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Processor / Low-Power / FPU / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 352, ICD2005-137, pp. 19-24, Oct. 2005. | |
| Paper # | ICD2005-137 | |
| Date of Issue | 2005-10-14 (SIP, ICD, IE) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2005-137 |
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| Conference Information | |
| Committee | SIP ICD IE IPSJ-SLDM |
| Conference Date | 2005-10-20 - 2005-10-21 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Ichinobo, Sakunami-Spa |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Processor, DSP, Image Engineering and etc. |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2005-10-SIP-ICD-IE-IPSJ-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Development of an embedded processor core SH-X2 |
| Sub Title (in English) | |
| Keyword(1) | Processor |
| Keyword(2) | Low-Power |
| Keyword(3) | FPU |
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| 1st Author's Name | Takashi Okada |
| 1st Author's Affiliation | Hitachi Ltd (Hitachi) |
| 2nd Author's Name | Tomoichi Hayashi |
| 2nd Author's Affiliation | Renesas Technology Corp (Renesas) |
| 3rd Author's Name | Takehiro Shimizu |
| 3rd Author's Affiliation | Renesas Technology Corp (Renesas) |
| 4th Author's Name | Fumio Arakawa |
| 4th Author's Affiliation | Hitachi Ltd (Hitachi) |
| 5th Author's Name | Tetsuya Yamada |
| 5th Author's Affiliation | Hitachi Ltd (Hitachi) |
| 6th Author's Name | Osamu Nishii |
| 6th Author's Affiliation | Renesas Technology Corp (Renesas) |
| 7th Author's Name | Toshihiro Hattori |
| 7th Author's Affiliation | Renesas Technology Corp (Renesas) |
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| Speaker | Author-1 |
| Date Time | 2005-10-21 10:10:00 |
| Presentation Time | 20 minutes |
| Registration for | ICD |
| Paper # | SIP2005-118, ICD2005-137, IE2005-82 |
| Volume (vol) | vol.105 |
| Number (no) | no.350(SIP), no.352(ICD), no.354(IE) |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2005-10-14 (SIP, ICD, IE) |
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