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| Presentation | 2005-12-22 14:25 Optimization of poly-Si TFT for controlling field emitter arrays Chiaki Yasumuro, Yuuichi Sakamura, Masayoshi Nagao, Hisao Tanoue, Seigo Kanemaru, Junji Itoh (AIST) Link to ES Tech. Rep. Archives:  ED2005-186 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | We have already proposed thin-film transistor (TFT) controlled field emitter arrays (FEAs) to improve uniformity of field emission display. The important features of the TFT for emission control are high withstand voltage, kink free, and low off leakage current. In this article, the structure of poly-Si TFT was optimized in the view point of controlling field emission current. The multi-gate structure, lightly-doped drain (LDD) structure, and their combination were tested. We found that the channel length should be more than 50 um for kink free characteristics and that the combination of multi-gate and LDD structure is effective for high withstand voltage and low off current. By using this optimized structure, the TFT-controlled FEA was fabricated and successfully operated. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Vacuum nano-electronics / field emission display / field emitter array / poly-Si TFT / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 105, no. 498, ED2005-186, pp. 21-26, Dec. 2005. | |
| Paper # | ED2005-186 | |
| Date of Issue | 2005-12-15 (ED) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ED2005-186 |
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| Conference Information | |
| Committee | ED |
| Conference Date | 2005-12-22 - 2005-12-22 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | |
| Paper Information | |
| Registration To | ED |
| Conference Code | 2005-12-ED |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Optimization of poly-Si TFT for controlling field emitter arrays |
| Sub Title (in English) | |
| Keyword(1) | Vacuum nano-electronics |
| Keyword(2) | field emission display |
| Keyword(3) | field emitter array |
| Keyword(4) | poly-Si TFT |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Chiaki Yasumuro |
| 1st Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
| 2nd Author's Name | Yuuichi Sakamura |
| 2nd Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
| 3rd Author's Name | Masayoshi Nagao |
| 3rd Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
| 4th Author's Name | Hisao Tanoue |
| 4th Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
| 5th Author's Name | Seigo Kanemaru |
| 5th Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
| 6th Author's Name | Junji Itoh |
| 6th Author's Affiliation | National Institute of Advanced Industrial Science and Technology (AIST) |
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| Speaker | Author-1 |
| Date Time | 2005-12-22 14:25:00 |
| Presentation Time | 25 minutes |
| Registration for | ED |
| Paper # | ED2005-186 |
| Volume (vol) | vol.105 |
| Number (no) | no.498 |
| Page | pp.21-26 |
| #Pages | 6 |
| Date of Issue | 2005-12-15 (ED) |
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