Paper Abstract and Keywords |
Presentation |
2006-08-18 14:35
A 65 nm SoC Embedded 6T-SRAM Design for Manufacturing with Read and Write Cell Stabilizing Circuits Makoto Yabuuchi, Shigeki Ohbayashi, Koji Nii, Yasumasa Tsukamoto (Renesas Technology), Susumu Imaoka (Renesas Design), Motoshige Igarashi, Masahiko Takeuchi, Hiroshi Kawashima, Hiroshi Makino, Yasuo Yamaguchi, Kazuhiro Tsukamoto, Masahide Inuishi, Koichiro Ishibashi, Hirofumi Shinohara (Renesas Technology) Link to ES Tech. Rep. Archives: SDM2006-151 ICD2006-105 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
(Not available yet) |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
/ / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 106, no. 207, ICD2006-105, pp. 149-153, Aug. 2006. |
Paper # |
ICD2006-105 |
Date of Issue |
2006-08-10 (SDM, ICD) |
ISSN |
Print edition: ISSN 0913-5685 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
Link to ES Tech. Rep. Archives: SDM2006-151 ICD2006-105 |
|