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Paper Abstract and Keywords
Presentation 2006-12-04 17:05
Linear-Size Log-Depth Negation-Limited Inverter for k-tonic 0/1 Sequences
Hiroki Morizumi (Kyoto Univ.), Jun Tarui (Univ. of Electro-Comm.)
Abstract (in Japanese) (See Japanese page) 
(in English) A binary sequence $x_1, \ldots, x_n$ is called $k$-tonic if for $1 \leq i \leq n-1$ the number of $i$'s such that $x_i \neq x_{i+1}$ is at most $k$. In this paper, we give the construction of a circuit inverting $k$-tonic sequences, which has size $O((\log k) \cdot n)$ depth $O((\log k) \cdot \log \log n + \log n)$ and contains $\log_2 n + O(\log\log n)$ NOT gates. Our construction improves all parameters of the construction by Sato, Amano and Maruoka, whose size is $O(kn)$ and depth is $O(k\log^{2}n)$ using $O(k\log n)$ NOT gates. If $k = O(1)$, the previous construction needs $O(\log^{2}n)$ depth, but our inverter has linear size and log depth using $O(\log n)$ NOT gates. Beals, Nishino and Tanaka have shown the construction of a size $O(n\log n)$ depth $O(\log n)$ inverter for all sequences with $\lceil \log_2(n+1) \rceil$ NOT gates. If $k=n^{o(1)}$, our construction reduces the size to $o(n\log n)$ with the same depth and only $O(\log\log n)$ increase of the number of NOT gates. Our idea on the construction of an inverter for $k$-tonic sequences also give an improvement for a circuit sorting $k$-tonic sequences from the construction by Sato, Amano and Maruoka.
Keyword (in Japanese) (See Japanese page) 
(in English) Circuit Complexity / Negation-Limited Circuit / Inverter / Sorter / $k$-tonic / / /  
Reference Info. IEICE Tech. Rep., vol. 106, no. 405, COMP2006-49, pp. 57-60, Dec. 2006.
Paper # COMP2006-49 
Date of Issue 2006-11-27 (COMP) 
ISSN Print edition: ISSN 0913-5685
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Conference Information
Committee COMP  
Conference Date 2006-12-04 - 2006-12-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Nagoya University 
Topics (in Japanese) (See Japanese page) 
Topics (in English)  
Paper Information
Registration To COMP 
Conference Code 2006-12-COMP 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Linear-Size Log-Depth Negation-Limited Inverter for k-tonic 0/1 Sequences 
Sub Title (in English)  
Keyword(1) Circuit Complexity  
Keyword(2) Negation-Limited Circuit  
Keyword(3) Inverter  
Keyword(4) Sorter  
Keyword(5) $k$-tonic  
1st Author's Name Hiroki Morizumi  
1st Author's Affiliation Kyoto University (Kyoto Univ.)
2nd Author's Name Jun Tarui  
2nd Author's Affiliation University of Electro-Communications (Univ. of Electro-Comm.)
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Date Time 2006-12-04 17:05:00 
Presentation Time 30 minutes 
Registration for COMP 
Paper # COMP2006-49 
Volume (vol) vol.106 
Number (no) no.405 
Page pp.57-60 
Date of Issue 2006-11-27 (COMP) 

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