Paper Abstract and Keywords |
Presentation |
2007-01-17 16:50
Converting PLC instruction sequence into logic circuit: implementation and evaluation Masanori Akinaka, Shuichi Ichikawa (Toyohashi Univ. Tech.) |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
By implementing a control program with hard-wired logic using reconfigurable devices (e.g., FPGA), a flexible and highly responsive system can be realized. This new system also contributes to securing intellectual property, while reducing implementation space and cost. This study outlines a converter that translates PLC instruction sequence into logic description. A productive ladder program was examined with Mitsubishi Electric FX2N PLC and Altera Stratix II FPGA, where a straightforward Sequential design (SD) was estimated to be 1800 times faster than PLC, while a performance-oriented Flat design (FD) was estimated to be 5.6 times faster than SD (i.e., 10000 times faster than PLC). Logic scales were 3554 ALUT for SD and 2643 ALUT for FD, which are small enough to fit into a state-of-the-art FPGA chip. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Programmable Logic Controller (PLC) / Field Programmable Gate Array (FPGA) / control program / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 106, no. 455, CPSY2006-63, pp. 43-48, Jan. 2007. |
Paper # |
CPSY2006-63 |
Date of Issue |
2007-01-10 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 |
Download PDF |
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Conference Information |
Committee |
VLD CPSY RECONF IPSJ-SLDM |
Conference Date |
2007-01-17 - 2007-01-18 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Keio Univ. Hiyoshi Campus |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
FPGA and its Application, etc. |
Paper Information |
Registration To |
CPSY |
Conference Code |
2007-01-VLD-CPSY-RECONF-IPSJ-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Converting PLC instruction sequence into logic circuit: implementation and evaluation |
Sub Title (in English) |
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Keyword(1) |
Programmable Logic Controller (PLC) |
Keyword(2) |
Field Programmable Gate Array (FPGA) |
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control program |
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1st Author's Name |
Masanori Akinaka |
1st Author's Affiliation |
Toyohashi University of Technology (Toyohashi Univ. Tech.) |
2nd Author's Name |
Shuichi Ichikawa |
2nd Author's Affiliation |
Toyohashi University of Technology (Toyohashi Univ. Tech.) |
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Speaker |
Author-1 |
Date Time |
2007-01-17 16:50:00 |
Presentation Time |
25 minutes |
Registration for |
CPSY |
Paper # |
VLD2006-92, CPSY2006-63, RECONF2006-63 |
Volume (vol) |
vol.106 |
Number (no) |
no.453(VLD), no.455(CPSY), no.457(RECONF) |
Page |
pp.43-48 |
#Pages |
6 |
Date of Issue |
2007-01-10 (VLD, CPSY, RECONF) |