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| Presentation | 2007-03-09 16:20 Statistical Delay Computation of Path-Based Timing Analysis Considering Inter and Intra-Chip Variations Katsumi Homma, Izumi Nitta, Toshiyuki Shibuya (Fujitsu Labs.) Link to ES Tech. Rep. Archives:  ICD2006-247 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Statistical Timing Analysis(SSTA) is a method that calculates circuit delay statistically with process variations. In SSTA, the delay variations are divided into intra-die and inter die variations. Intra-die variations are independent for each cells and lines in a chip. Inter-chip variations are governed by one variation on a chip. In this paper, we propose a new method of computing whole chip delay distribution considering inter and intra-chip variations in path-based SSTA. In practical LSI data experiments, it is confirmed that the propose method is more accurate than previous methods. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Statistical Static Timing Analysis / Intra-die variations / Inter-die variations / Path-based Analysis / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 106, no. 549, VLD2006-156, pp. 93-98, March 2007. | |
| Paper # | VLD2006-156 | |
| Date of Issue | 2007-03-02 (VLD, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2006-247 |
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| Conference Information | |
| Committee | ICD VLD |
| Conference Date | 2007-03-07 - 2007-03-09 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Mielparque Okinawa |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System-on-silicon design techniques and related VLSs |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2007-03-ICD-VLD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Statistical Delay Computation of Path-Based Timing Analysis Considering Inter and Intra-Chip Variations |
| Sub Title (in English) | |
| Keyword(1) | Statistical Static Timing Analysis |
| Keyword(2) | Intra-die variations |
| Keyword(3) | Inter-die variations |
| Keyword(4) | Path-based Analysis |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Katsumi Homma |
| 1st Author's Affiliation | Fujitsu Laboratries Ltd. (Fujitsu Labs.) |
| 2nd Author's Name | Izumi Nitta |
| 2nd Author's Affiliation | Fujitsu Laboratries Ltd. (Fujitsu Labs.) |
| 3rd Author's Name | Toshiyuki Shibuya |
| 3rd Author's Affiliation | Fujitsu Laboratries Ltd. (Fujitsu Labs.) |
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| Speaker | Author-1 |
| Date Time | 2007-03-09 16:20:00 |
| Presentation Time | 20 minutes |
| Registration for | VLD |
| Paper # | VLD2006-156, ICD2006-247 |
| Volume (vol) | vol.106 |
| Number (no) | no.549(VLD), no.552(ICD) |
| Page | pp.93-98 |
| #Pages | 6 |
| Date of Issue | 2007-03-02 (VLD, ICD) |
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