Paper Abstract and Keywords |
Presentation |
2007-05-10 13:30
Memory Assignment Method for Matrix Processing Array Akira Kobashi, Ittetsu Taniguchi, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai (Osaka Univ.), Kiyoshi Nakata (Renesas) VLD2007-1 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
MTA (MaTrix processing Array), which is developed by Renesas Technology Corp., can achieve high performance for digital signal processing using its high parallelism.However, the execution cycles of MTA greatly change by the data assignment for the internal memories. In this paper, we propose a data assignment optimization method for MTA. Experimental results show that proposed method can reduce overhead about 96% in the case of DCT. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Combinatorial optimization / Memory assignment / Maximum cut problem / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 31, VLD2007-1, pp. 1-6, May 2007. |
Paper # |
VLD2007-1 |
Date of Issue |
2007-05-03 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2007-1 |
Conference Information |
Committee |
VLD IPSJ-SLDM |
Conference Date |
2007-05-10 - 2007-05-11 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kyodai Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
System Design, etc. |
Paper Information |
Registration To |
VLD |
Conference Code |
2007-05-VLD-IPSJ-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Memory Assignment Method for Matrix Processing Array |
Sub Title (in English) |
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Keyword(1) |
Combinatorial optimization |
Keyword(2) |
Memory assignment |
Keyword(3) |
Maximum cut problem |
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1st Author's Name |
Akira Kobashi |
1st Author's Affiliation |
Osaka University (Osaka Univ.) |
2nd Author's Name |
Ittetsu Taniguchi |
2nd Author's Affiliation |
Osaka University (Osaka Univ.) |
3rd Author's Name |
Keishi Sakanushi |
3rd Author's Affiliation |
Osaka University (Osaka Univ.) |
4th Author's Name |
Yoshinori Takeuchi |
4th Author's Affiliation |
Osaka University (Osaka Univ.) |
5th Author's Name |
Masaharu Imai |
5th Author's Affiliation |
Osaka University (Osaka Univ.) |
6th Author's Name |
Kiyoshi Nakata |
6th Author's Affiliation |
Renesas Technology Corporation (Renesas) |
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Speaker |
Author-1 |
Date Time |
2007-05-10 13:30:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2007-1 |
Volume (vol) |
vol.107 |
Number (no) |
no.31 |
Page |
pp.1-6 |
#Pages |
6 |
Date of Issue |
2007-05-03 (VLD) |
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