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| Presentation | 2007-05-11 10:55 An Asynchronous Single-precision Floating-point Divider and its Implementation on FPGA Masayuki Hiromoto, Atsuko Takahashi, Shin'ichi Kouyama, Hiroyuki Ochi (Kyoto Univ.), Yukihiro Nakamura (Ritsumeikan Univ.)  VLD2007-10 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Synchronous design methodology is widely used for today's digital circuits. However, highly optimized synchronous design for a specific clock frequency is difficult to be reused in another system with different clock requency, because logic depth between FFs should be tailored for the clock requency. In this paper, we focus on \textit{Asynchronous} design, in which each module works at its best performance, and apply it to an IEEE754-standard single-precision floating-point divider. In our divider, a mantissa divider is driven by a high-speed local clock and connected to pre-/post-processing modules with asynchronous interface. Our divider is ready to be built into a system with arbitrary clock frequency and achieve its peak performance and area- and power-efficiency. This paper also reports an implementation result of the proposed divider on a Xilinx FPGA. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | IP reusability / IEEE754 / low power design / digit-recurrence divider / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 32, VLD2007-10, pp. 19-24, May 2007. | |
| Paper # | VLD2007-10 | |
| Date of Issue | 2007-05-04 (VLD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2007-10 |
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| Conference Information | |
| Committee | VLD IPSJ-SLDM |
| Conference Date | 2007-05-10 - 2007-05-11 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kyodai Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System Design, etc. |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2007-05-VLD-IPSJ-SLDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | An Asynchronous Single-precision Floating-point Divider and its Implementation on FPGA |
| Sub Title (in English) | |
| Keyword(1) | IP reusability |
| Keyword(2) | IEEE754 |
| Keyword(3) | low power design |
| Keyword(4) | digit-recurrence divider |
| Keyword(5) | |
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| Keyword(8) | |
| 1st Author's Name | Masayuki Hiromoto |
| 1st Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 2nd Author's Name | Atsuko Takahashi |
| 2nd Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 3rd Author's Name | Shin'ichi Kouyama |
| 3rd Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 4th Author's Name | Hiroyuki Ochi |
| 4th Author's Affiliation | Kyoto University (Kyoto Univ.) |
| 5th Author's Name | Yukihiro Nakamura |
| 5th Author's Affiliation | Ritsumeikan University (Ritsumeikan Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-05-11 10:55:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2007-10 |
| Volume (vol) | vol.107 |
| Number (no) | no.32 |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2007-05-04 (VLD) |
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