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| Presentation | 2007-05-31 14:15 A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption Kiyoshi Hayase, Yutaka Yoshida, Tatsuya Kamei, Shinichi Shibahara, Osamu Nishii, Toshihiro Hattori, Atsushi Hasegawa (Renesas technology), Masashi Takada, Naohiko Irie, Kunio Uchiyama, Toshihiko Odaka (Hitachi Ltd.), Kiwamu Takada (Hitachi ULSI Systems Co. Ltd.), Keiji Kimura, Hironori Kasahara (Waseda Univ.)  ICD2007-22 Link to ES Tech. Rep. Archives: ICD2007-22 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | 4320MIPS 4-processor SoC that provides with low power consumption and high performance was designed using 90nm process. The 32KB-data cache is built into each processor, and the module to maintain the coherency of the data cache between processors is built into. A low electric power is achieved by frequency control of each processor according to amount of processing and adopting sleep mode that maintains coherency of the data cache between processors. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | multi processor / individually managed clock frequency / cache coherency / MESI protocol / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 76, ICD2007-22, pp. 31-35, May 2007. | |
| Paper # | ICD2007-22 | |
| Date of Issue | 2007-05-24 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2007-22 Link to ES Tech. Rep. Archives: ICD2007-22 |
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| Conference Information | |
| Committee | ICD IPSJ-ARC |
| Conference Date | 2007-05-31 - 2007-06-01 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Creative Collaboration between Circuit and Architecture: Processor, Memory and SOC |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2007-05-ICD-IPSJ-ARC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A 4320MIPS Four-Processor Core SMP/AMP with Individually Managed Clock Frequency for Low Power Consumption |
| Sub Title (in English) | |
| Keyword(1) | multi processor |
| Keyword(2) | individually managed clock frequency |
| Keyword(3) | cache coherency |
| Keyword(4) | MESI protocol |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Kiyoshi Hayase |
| 1st Author's Affiliation | Renesas Technology Corp. (Renesas technology) |
| 2nd Author's Name | Yutaka Yoshida |
| 2nd Author's Affiliation | Renesas Technology Corp. (Renesas technology) |
| 3rd Author's Name | Tatsuya Kamei |
| 3rd Author's Affiliation | Renesas Technology Corp. (Renesas technology) |
| 4th Author's Name | Shinichi Shibahara |
| 4th Author's Affiliation | Renesas Technology Corp. (Renesas technology) |
| 5th Author's Name | Osamu Nishii |
| 5th Author's Affiliation | Renesas Technology Corp. (Renesas technology) |
| 6th Author's Name | Toshihiro Hattori |
| 6th Author's Affiliation | Renesas Technology Corp. (Renesas technology) |
| 7th Author's Name | Atsushi Hasegawa |
| 7th Author's Affiliation | Renesas Technology Corp. (Renesas technology) |
| 8th Author's Name | Masashi Takada |
| 8th Author's Affiliation | Hitachi Ltd. (Hitachi Ltd.) |
| 9th Author's Name | Naohiko Irie |
| 9th Author's Affiliation | Hitachi Ltd. (Hitachi Ltd.) |
| 10th Author's Name | Kunio Uchiyama |
| 10th Author's Affiliation | Hitachi Ltd. (Hitachi Ltd.) |
| 11th Author's Name | Toshihiko Odaka |
| 11th Author's Affiliation | Hitachi Ltd. (Hitachi Ltd.) |
| 12th Author's Name | Kiwamu Takada |
| 12th Author's Affiliation | 3Hitachi ULSI Systems Co., Ltd. (Hitachi ULSI Systems Co. Ltd.) |
| 13th Author's Name | Keiji Kimura |
| 13th Author's Affiliation | Waseda University (Waseda Univ.) |
| 14th Author's Name | Hironori Kasahara |
| 14th Author's Affiliation | Waseda University (Waseda Univ.) |
| 15th Author's Name | |
| 15th Author's Affiliation | () |
| 16th Author's Name | |
| 16th Author's Affiliation | () |
| 17th Author's Name | |
| 17th Author's Affiliation | () |
| 18th Author's Name | |
| 18th Author's Affiliation | () |
| Speaker | Author-1 |
| Date Time | 2007-05-31 14:15:00 |
| Presentation Time | 30 minutes |
| Registration for | ICD |
| Paper # | ICD2007-22 |
| Volume (vol) | vol.107 |
| Number (no) | no.76 |
| Page | pp.31-35 |
| #Pages | 5 |
| Date of Issue | 2007-05-24 (ICD) |
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