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| Presentation | 2007-06-01 11:00 Design Techniques of Wave Pipelines Masa-aki Fukase, Tomoaki Sato (Hirosaki Univ.)  ICD2007-28 Link to ES Tech. Rep. Archives: ICD2007-28 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In order to improve rather complicated design and testing methods of wave-pipelines, our policy is to cover rough tuning as well as fine tuning. This is practically useful for both universal chips and FPGAs. The reconfigurable feature of FPGAs is crucial for quickly corresponding to the drastic change of ubiquitous network environment. In this study, we have focused our attention to three key techniques. The first topic is the development of a CAD tool that dynamically shows a wave map. The second topic is the application of wave-pipelining to sequential circuits. The final topic is a double clocking scheme. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Wave-pipeline / sequential logic / design for testability / processor / chip / CMOS / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 76, ICD2007-28, pp. 67-72, May 2007. | |
| Paper # | ICD2007-28 | |
| Date of Issue | 2007-05-24 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ICD2007-28 Link to ES Tech. Rep. Archives: ICD2007-28 |
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| Conference Information | |
| Committee | ICD IPSJ-ARC |
| Conference Date | 2007-05-31 - 2007-06-01 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Creative Collaboration between Circuit and Architecture: Processor, Memory and SOC |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2007-05-ICD-IPSJ-ARC |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Design Techniques of Wave Pipelines |
| Sub Title (in English) | |
| Keyword(1) | Wave-pipeline |
| Keyword(2) | sequential logic |
| Keyword(3) | design for testability |
| Keyword(4) | processor |
| Keyword(5) | chip |
| Keyword(6) | CMOS |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Masa-aki Fukase |
| 1st Author's Affiliation | Hirosaki University (Hirosaki Univ.) |
| 2nd Author's Name | Tomoaki Sato |
| 2nd Author's Affiliation | Hirosaki University (Hirosaki Univ.) |
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| Speaker | Author-2 |
| Date Time | 2007-06-01 11:00:00 |
| Presentation Time | 30 minutes |
| Registration for | ICD |
| Paper # | ICD2007-28 |
| Volume (vol) | vol.107 |
| Number (no) | no.76 |
| Page | pp.67-72 |
| #Pages | 6 |
| Date of Issue | 2007-05-24 (ICD) |
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