Paper Abstract and Keywords |
Presentation |
2007-10-26 09:00
An examination of hardware acceleration in FPGA placement based on SA Yoshio Sonokawa, Yuji Ariuchi, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.) CPSY2007-30 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Placement is one of the steps that expend the time in the FPGA (Field Programmable Gate Array) design automation flow.
The scale-up of the implementing circuit advances, and the speed-up of the FPGA disposition becomes design automation by the performance improving of FPGA with an important problem because the required time increases rapidly in recent years.
In this paper, SA (Simulated Annealing) algorithm most widely used as a approximate analysis of the FPGA placement problem is imitated and the algorithm that is appropriate for hardware is adopted.
And, the speed-up of the FPGA disposition was examined by proposed hardware.
The evaluation made software that did processing similar to processing on hardware, and did the performance measurement by making to hardware with the simulator.
When having compared it with the result by VPR (Versatile Place and Route), it was understood to be able to achieve about 600-50 times the speedup even if 1.3-1.1 times cost increased. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
FPGA placement / parallel algorithm / hardware acceleration / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 276, CPSY2007-30, pp. 33-38, Oct. 2007. |
Paper # |
CPSY2007-30 |
Date of Issue |
2007-10-18 (CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2007-30 |
Conference Information |
Committee |
CPSY |
Conference Date |
2007-10-25 - 2007-10-26 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Kumamoto University |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Advanced Computer Systems, etc. |
Paper Information |
Registration To |
CPSY |
Conference Code |
2007-10-CPSY |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
An examination of hardware acceleration in FPGA placement based on SA |
Sub Title (in English) |
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Keyword(1) |
FPGA placement |
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parallel algorithm |
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hardware acceleration |
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1st Author's Name |
Yoshio Sonokawa |
1st Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
2nd Author's Name |
Yuji Ariuchi |
2nd Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
3rd Author's Name |
Morihiro Kuga |
3rd Author's Affiliation |
Kumamoto University (Kumamoto Univ.) |
4th Author's Name |
Toshinori Sueyoshi |
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Kumamoto University (Kumamoto Univ.) |
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Speaker |
Author-1 |
Date Time |
2007-10-26 09:00:00 |
Presentation Time |
40 minutes |
Registration for |
CPSY |
Paper # |
CPSY2007-30 |
Volume (vol) |
vol.107 |
Number (no) |
no.276 |
Page |
pp.33-38 |
#Pages |
6 |
Date of Issue |
2007-10-18 (CPSY) |
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