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| Presentation | 2007-12-14 11:00 Analysis of Capacitance-Voltage Characteristics of Poly-Si TFTs using Device Simulation Tsuyoshi Kuzuoka, Hiroshi Tsuji, Masaharu Kirihara, Yoshinari Kamakura, Kenji Taniguchi (Osaka Univ.)  SDM2007-225 Link to ES Tech. Rep. Archives: SDM2007-225 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Capacitance-voltage characteristics of short channel Poly-Si TFTs containing only a single grain boundary were investigated using a two-dimensional device simulator. It was demonstrated that the drain/source charge partition is significantly affected by the position of the grain boundary, which results in the asymmetric characteristics of the gate-to-source (Cgs) and the gate-to-drain (Cgd) capacitances even if no bias is applied between source and drain. We discuss the mechanisms of the asymmetric charge partition caused by the grain boundary by analyzing the internal physical quantities in TFTs (potential, carrier density distribution, etc.) using the device simulations. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | polysilicon / TFT / grain boundary / device simulation / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 388, SDM2007-225, pp. 15-18, Dec. 2007. | |
| Paper # | SDM2007-225 | |
| Date of Issue | 2007-12-07 (SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | SDM2007-225 Link to ES Tech. Rep. Archives: SDM2007-225 |
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| Conference Information | |
| Committee | SDM |
| Conference Date | 2007-12-14 - 2007-12-14 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Nara Institute Science and Technology |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Silicon related material, process and device |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2007-12-SDM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Analysis of Capacitance-Voltage Characteristics of Poly-Si TFTs using Device Simulation |
| Sub Title (in English) | |
| Keyword(1) | polysilicon |
| Keyword(2) | TFT |
| Keyword(3) | grain boundary |
| Keyword(4) | device simulation |
| Keyword(5) | |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Tsuyoshi Kuzuoka |
| 1st Author's Affiliation | Osaka University (Osaka Univ.) |
| 2nd Author's Name | Hiroshi Tsuji |
| 2nd Author's Affiliation | Osaka University (Osaka Univ.) |
| 3rd Author's Name | Masaharu Kirihara |
| 3rd Author's Affiliation | Osaka University (Osaka Univ.) |
| 4th Author's Name | Yoshinari Kamakura |
| 4th Author's Affiliation | Osaka University (Osaka Univ.) |
| 5th Author's Name | Kenji Taniguchi |
| 5th Author's Affiliation | Osaka University (Osaka Univ.) |
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| Speaker | Author-1 |
| Date Time | 2007-12-14 11:00:00 |
| Presentation Time | 20 minutes |
| Registration for | SDM |
| Paper # | SDM2007-225 |
| Volume (vol) | vol.107 |
| Number (no) | no.388 |
| Page | pp.15-18 |
| #Pages | 4 |
| Date of Issue | 2007-12-07 (SDM) |
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