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| Presentation | 2008-03-05 13:25 Task Scheduling Technique for Mitigating SEU Vulnerability of Heterogeneous Multiprocessor Systems Makoto Sugihara (TUT)  VLD2007-138 ICD2007-161 Link to ES Tech. Rep. Archives: ICD2007-161 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Utilizing a heterogeneous multiprocessor system has become a popular design paradigm to build an embedded system at a cheap cost within short development time. A reliability issue for embedded systems, which is vulnerability to single event upsets (SEUs), has become a matter of concern as technology proceeds. This paper presents robustness of heterogeneous multiprocessors to SEUs and proposes task scheduling for minimizing SEU vulnerability of them. This paper experimentally shows that increasing performance of a CPU core deteriorates its reliability. Based on the experimental observation, we propose task scheduling for reducing SEU vulnerability of a heterogeneous multiprocessor system. The experimental results demonstrate that our task scheduling technique can reduce much of SEU vulnerability under real-time constraints. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Single Event Upset / Soft Error / Reliability / Performance / Vulnerability / Cache Memory / Task Scheduling / Heterogeneous Multiprocessor | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 506, VLD2007-138, pp. 7-12, March 2008. | |
| Paper # | VLD2007-138 | |
| Date of Issue | 2008-02-27 (VLD, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2007-138 ICD2007-161 Link to ES Tech. Rep. Archives: ICD2007-161 |
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| Conference Information | |
| Committee | VLD ICD |
| Conference Date | 2008-03-05 - 2008-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | TiRuRu |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System-on-silicon design techniques and related VLSs |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2008-03-VLD-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Task Scheduling Technique for Mitigating SEU Vulnerability of Heterogeneous Multiprocessor Systems |
| Sub Title (in English) | |
| Keyword(1) | Single Event Upset |
| Keyword(2) | Soft Error |
| Keyword(3) | Reliability |
| Keyword(4) | Performance |
| Keyword(5) | Vulnerability |
| Keyword(6) | Cache Memory |
| Keyword(7) | Task Scheduling |
| Keyword(8) | Heterogeneous Multiprocessor |
| 1st Author's Name | Makoto Sugihara |
| 1st Author's Affiliation | Toyohashi University of Technology (TUT) |
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| Speaker | Author-1 |
| Date Time | 2008-03-05 13:25:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2007-138, ICD2007-161 |
| Volume (vol) | vol.107 |
| Number (no) | no.506(VLD), no.509(ICD) |
| Page | pp.7-12 |
| #Pages | 6 |
| Date of Issue | 2008-02-27 (VLD, ICD) |
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