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Paper Abstract and Keywords
Presentation 2008-03-06 16:10
Global Routing Method of Plating Lead for 2-Layer BGA Packages
Naoki Sato, Yoichi Tomioka, Atsushi Takahashi (Tokyo Tech) VLD2007-154 ICD2007-177 Link to ES Tech. Rep. Archives: ICD2007-177
Abstract (in Japanese) (See Japanese page) 
(in English) In this paper, we propose a global routing method for 2-layer BGA packages
in which the layer assignment of plating leads is determined.
For a given via assignment,
our method determines the layer assignment of plating leads
so that the violations of wire congestion in layer-1 are reduced
while maintaining the connections in layer-2.
In our proposed method,
first, all plating leads are assigned to layer-1.
Then, the layer assignment of a set of plating leads,
each of which passes through a violated region,
is repeatedly changed to layer-2.
In each repetition,
a set of plating leads
that can reduce the violations of wire congestion in layer-1 evenly
and that can keep the connections in layer-2
is selected.
In experiments with several data,
we confirm that
our proposed method efficiently improves routing pattern
so that the violations in layer-1 are reduced
while maintaining the connections in layer-2.
Keyword (in Japanese) (See Japanese page) 
(in English) package routing / BGA packages / plating leads / layer assignment / / / /  
Reference Info. IEICE Tech. Rep., vol. 107, no. 507, VLD2007-154, pp. 61-66, March 2008.
Paper # VLD2007-154 
Date of Issue 2008-02-28 (VLD, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2007-154 ICD2007-177 Link to ES Tech. Rep. Archives: ICD2007-177

Conference Information
Committee VLD ICD  
Conference Date 2008-03-05 - 2008-03-07 
Place (in Japanese) (See Japanese page) 
Place (in English) TiRuRu 
Topics (in Japanese) (See Japanese page) 
Topics (in English) System-on-silicon design techniques and related VLSs 
Paper Information
Registration To VLD 
Conference Code 2008-03-VLD-ICD 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Global Routing Method of Plating Lead for 2-Layer BGA Packages 
Sub Title (in English)  
Keyword(1) package routing  
Keyword(2) BGA packages  
Keyword(3) plating leads  
Keyword(4) layer assignment  
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1st Author's Name Naoki Sato  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
2nd Author's Name Yoichi Tomioka  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
3rd Author's Name Atsushi Takahashi  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Tech)
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Speaker Author-1 
Date Time 2008-03-06 16:10:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2007-154, ICD2007-177 
Volume (vol) vol.107 
Number (no) no.507(VLD), no.510(ICD) 
Page pp.61-66 
#Pages
Date of Issue 2008-02-28 (VLD, ICD) 


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