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| Presentation | 2008-03-06 09:15 A Design of High Accuracy and Low Power Cyclic ADC using Digital Calibration Tetsuro Ikeda, Atsushi Iwata (Hiroshima Univ.)  VLD2007-144 ICD2007-167 Link to ES Tech. Rep. Archives: ICD2007-167 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | This paper proposes a high-accuracy and low-power cyclic ADC using digital calibration technique. By using a cascaded cyclic ADC, we can reduce an operation speed of unit circuit and power consumption. To acieve high accuracy, new digital calibration algorithm to compensate capacitance mismatch of a switched capacitor gain stage was proposed. Utilizing the propsed ADC architecture, a 2-stage cyclic ADC with 16 bit resolution was designed using a 0.18 $\mu$m CMOS technology. The ADC opeartes at 500 kS/s sampling rate with 20 mW power dissipation. The efffects of digtal calibration was confirmed by simulation. A calibrated Integral Non Linearity (INL) was about $\pm$3 LSB of 16 bit. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Cyclic ADC / Switched capacitor circuit / Digital calibration / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 510, ICD2007-167, pp. 1-6, March 2008. | |
| Paper # | ICD2007-167 | |
| Date of Issue | 2008-02-28 (VLD, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2007-144 ICD2007-167 Link to ES Tech. Rep. Archives: ICD2007-167 |
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| Conference Information | |
| Committee | VLD ICD |
| Conference Date | 2008-03-05 - 2008-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | TiRuRu |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System-on-silicon design techniques and related VLSs |
| Paper Information | |
| Registration To | ICD |
| Conference Code | 2008-03-VLD-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Design of High Accuracy and Low Power Cyclic ADC using Digital Calibration |
| Sub Title (in English) | |
| Keyword(1) | Cyclic ADC |
| Keyword(2) | Switched capacitor circuit |
| Keyword(3) | Digital calibration |
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| 1st Author's Name | Tetsuro Ikeda |
| 1st Author's Affiliation | Hiroshima University (Hiroshima Univ.) |
| 2nd Author's Name | Atsushi Iwata |
| 2nd Author's Affiliation | Hiroshima University (Hiroshima Univ.) |
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| Speaker | Author-1 |
| Date Time | 2008-03-06 09:15:00 |
| Presentation Time | 25 minutes |
| Registration for | ICD |
| Paper # | VLD2007-144, ICD2007-167 |
| Volume (vol) | vol.107 |
| Number (no) | no.507(VLD), no.510(ICD) |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2008-02-28 (VLD, ICD) |
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