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| Presentation | 2008-03-06 12:00 Area/Delay/Power Consumption Tradeoff for Multiplier with Tree-structured Partial-product Adders Masayoshi Tachibana (kochi University of Technology)  VLD2007-150 ICD2007-173 Link to ES Tech. Rep. Archives: ICD2007-173 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | In this paper we address the area, delay and power consumption tradeoff for multiplier with tree-structured partial product adders. It is well known that a distinctive delay profile of partial product adder makes tradeoff between delay and area of final stage adders. In this paper, we report that tradeoff between power consumption and area or delay also exist because power consumption of adders varied greatly by very little input arrival time variation, and propose a optimizing method for required multiplier performance. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Multiplier / Power consumption / Dadda tree / Wallace tree / Final stage adders / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 107, no. 507, VLD2007-150, pp. 37-42, March 2008. | |
| Paper # | VLD2007-150 | |
| Date of Issue | 2008-02-28 (VLD, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | VLD2007-150 ICD2007-173 Link to ES Tech. Rep. Archives: ICD2007-173 |
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| Conference Information | |
| Committee | VLD ICD |
| Conference Date | 2008-03-05 - 2008-03-07 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | TiRuRu |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | System-on-silicon design techniques and related VLSs |
| Paper Information | |
| Registration To | VLD |
| Conference Code | 2008-03-VLD-ICD |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Area/Delay/Power Consumption Tradeoff for Multiplier with Tree-structured Partial-product Adders |
| Sub Title (in English) | |
| Keyword(1) | Multiplier |
| Keyword(2) | Power consumption |
| Keyword(3) | Dadda tree |
| Keyword(4) | Wallace tree |
| Keyword(5) | Final stage adders |
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| 1st Author's Name | Masayoshi Tachibana |
| 1st Author's Affiliation | kochi University of Technology (kochi University of Technology) |
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| Speaker | Author-1 |
| Date Time | 2008-03-06 12:00:00 |
| Presentation Time | 25 minutes |
| Registration for | VLD |
| Paper # | VLD2007-150, ICD2007-173 |
| Volume (vol) | vol.107 |
| Number (no) | no.507(VLD), no.510(ICD) |
| Page | pp.37-42 |
| #Pages | 6 |
| Date of Issue | 2008-02-28 (VLD, ICD) |
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