Paper Abstract and Keywords |
Presentation |
2008-03-07 11:10
Design of High-rate Irregular LDPC Decoder based on Accelerated Message-passing Schedule Yuta Abe, Naoki Tajima, Xing Li, Kazunori Shimizu, Takeshi Ikenaga, Satoshi Goto (Waseda Univ.) VLD2007-160 ICD2007-183 Link to ES Tech. Rep. Archives: ICD2007-183 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, We Design of High Throughput Multi-rate Irregular LDPC Decoder based on Accelerated Message-Passing Schedule. The irregular LDPC decoder which adopts high-efficiency message passing method is reported in Ref.[9], however Ref.[9] has problem. LDPC decoder of Ref.[9] has only 54Mbps processing speed even though the request speed of IEEE802.11n is 330Mbps (Code rate is 1/2). In addition, The code-rate of IEEE802.11n has number of 4 code-rate(1/2, 2/3, 3/4 5/6). Then in this paper, we propose high-throughput and multi-rate method for The irregular LDPC decoder. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
LDPC / / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 511, ICD2007-183, pp. 25-30, March 2008. |
Paper # |
ICD2007-183 |
Date of Issue |
2008-02-29 (VLD, ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2007-160 ICD2007-183 Link to ES Tech. Rep. Archives: ICD2007-183 |
Conference Information |
Committee |
VLD ICD |
Conference Date |
2008-03-05 - 2008-03-07 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
TiRuRu |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
System-on-silicon design techniques and related VLSs |
Paper Information |
Registration To |
ICD |
Conference Code |
2008-03-VLD-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Design of High-rate Irregular LDPC Decoder based on Accelerated Message-passing Schedule |
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LDPC |
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1st Author's Name |
Yuta Abe |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Naoki Tajima |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Xing Li |
3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
4th Author's Name |
Kazunori Shimizu |
4th Author's Affiliation |
Waseda University (Waseda Univ.) |
5th Author's Name |
Takeshi Ikenaga |
5th Author's Affiliation |
Waseda University (Waseda Univ.) |
6th Author's Name |
Satoshi Goto |
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Waseda University (Waseda Univ.) |
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Speaker |
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Date Time |
2008-03-07 11:10:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
VLD2007-160, ICD2007-183 |
Volume (vol) |
vol.107 |
Number (no) |
no.508(VLD), no.511(ICD) |
Page |
pp.25-30 |
#Pages |
6 |
Date of Issue |
2008-02-29 (VLD, ICD) |
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