Paper Abstract and Keywords |
Presentation |
2008-03-27 09:30
Function and Efficiency Enhancement of A Simulation Environment with Multiprocessor RTOS Hiroshi Aiba, Seiya Shibata, Takashi Furukawa, Shinya Honda, Hiroyuki Tomiyama, Hiroaki Takada (Nagoya Univ.) DC2007-86 CPSY2007-82 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper presents two improvement techniques which we have applied for our multiprocessor simulation environment with multiple ISSs. In this simulation environment, Multiple ISSs are executed without synchronization.
In order to validate the timing correctness of communications performed between ISSs, first improvement technique provides cycle level synchronization mechanisms to ISSs. Another one reduces simulation time by using host CPU efficiently, considering RTOS's idle state. When synchronizing ISSs every 1000 cycles, this improvement reduced simulation time of MPEG4 decoder by 40$\%$. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
simulation / multiprocessor / RTOS / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 107, no. 559, DC2007-86, pp. 13-18, March 2008. |
Paper # |
DC2007-86 |
Date of Issue |
2008-03-20 (DC, CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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DC2007-86 CPSY2007-82 |
Conference Information |
Committee |
DC CPSY IPSJ-SLDM IPSJ-EMB |
Conference Date |
2008-03-27 - 2008-03-28 |
Place (in Japanese) |
(See Japanese page) |
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(See Japanese page) |
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Paper Information |
Registration To |
DC |
Conference Code |
2008-03-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Function and Efficiency Enhancement of A Simulation Environment with Multiprocessor RTOS |
Sub Title (in English) |
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Keyword(1) |
simulation |
Keyword(2) |
multiprocessor |
Keyword(3) |
RTOS |
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1st Author's Name |
Hiroshi Aiba |
1st Author's Affiliation |
Nagoya University (Nagoya Univ.) |
2nd Author's Name |
Seiya Shibata |
2nd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
3rd Author's Name |
Takashi Furukawa |
3rd Author's Affiliation |
Nagoya University (Nagoya Univ.) |
4th Author's Name |
Shinya Honda |
4th Author's Affiliation |
Nagoya University (Nagoya Univ.) |
5th Author's Name |
Hiroyuki Tomiyama |
5th Author's Affiliation |
Nagoya University (Nagoya Univ.) |
6th Author's Name |
Hiroaki Takada |
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Nagoya University (Nagoya Univ.) |
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Speaker |
Author-1 |
Date Time |
2008-03-27 09:30:00 |
Presentation Time |
20 minutes |
Registration for |
DC |
Paper # |
DC2007-86, CPSY2007-82 |
Volume (vol) |
vol.107 |
Number (no) |
no.559(DC), no.558(CPSY) |
Page |
pp.13-18 |
#Pages |
6 |
Date of Issue |
2008-03-20 (DC, CPSY) |
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