Paper Abstract and Keywords |
Presentation |
2008-06-27 09:20
Safe Clocking Minimum Register Assignment in High-Level Synthesis Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki (JAIST) CAS2008-20 VLD2008-33 SIP2008-54 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
For recent and future nanometer-technology VLSIs,
static and dynamic delay variations become a serious problem.
In many cases, the hold constraint, as well as the setup constraint, becomes critical for latching a correct signal under delay variations. Our approach to delay variation (in particular, the hold constraint) proposed in this paper is a novel register assignment strategy in high-level synthesis, which guarantees safe clocking by the contra-data-direction (CDD) clocking. After formulating this new register assignment problem, we prove it to be NP-hard, and then derive an integer linear programming formulation for the problem. The proposed method receives a scheduled data flow graph, and generates a datapath having (1) robustness against delay variations, which is ensured by CDD-based register assignment, and (2) the minimum possible number of registers. Experimental results show the effectiveness of the proposed method for some benchmark circuits. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
High-level synthesis / hold constraint / safe clocking / register assignment / integer linear programming / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 105, CAS2008-20, pp. 7-12, June 2008. |
Paper # |
CAS2008-20 |
Date of Issue |
2008-06-20 (CAS, VLD, SIP) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CAS2008-20 VLD2008-33 SIP2008-54 |
Conference Information |
Committee |
VLD CAS SIP |
Conference Date |
2008-06-26 - 2008-06-27 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Hokkaido Univ. |
Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
CAS |
Conference Code |
2008-06-VLD-CAS-SIP |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Safe Clocking Minimum Register Assignment in High-Level Synthesis |
Sub Title (in English) |
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Keyword(1) |
High-level synthesis |
Keyword(2) |
hold constraint |
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safe clocking |
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register assignment |
Keyword(5) |
integer linear programming |
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1st Author's Name |
Keisuke Inoue |
1st Author's Affiliation |
Japan Advanced Institute of Science and Technology (JAIST) |
2nd Author's Name |
Mineo Kaneko |
2nd Author's Affiliation |
Japan Advanced Institute of Science and Technology (JAIST) |
3rd Author's Name |
Tsuyoshi Iwagaki |
3rd Author's Affiliation |
Japan Advanced Institute of Science and Technology (JAIST) |
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Speaker |
Author-1 |
Date Time |
2008-06-27 09:20:00 |
Presentation Time |
20 minutes |
Registration for |
CAS |
Paper # |
CAS2008-20, VLD2008-33, SIP2008-54 |
Volume (vol) |
vol.108 |
Number (no) |
no.105(CAS), no.107(VLD), no.109(SIP) |
Page |
pp.7-12 |
#Pages |
6 |
Date of Issue |
2008-06-20 (CAS, VLD, SIP) |
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