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| Presentation | 2008-07-11 15:05 24 GHz Low Noise Amplifier Design in 65 nm CMOS Technology with Inter-Stage Matching Optimization Ickhyun Song, Hakchul Jung, Hee-Sauk Jhon, Minsuk Koo, Hyungcheol Shin (Seoul National Univ.)  ED2008-96 SDM2008-115 Link to ES Tech. Rep. Archives: ED2008-96 SDM2008-115 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | 2-stage 24 GHz low noise amplifier (LNA) was designed using 65 nm RF CMOS technology. Since conventional topology with inductive source degeneration provides lower signal gain at 24 GHz, a source inductor is eliminated and therefore, modified structure in which a shunt inductor was used for input matching is adopted. Figure of merit (FoM) which includes gain, noise figure, and power consumption was used as a design criterion and was maximized considering various circuit parameters such as transistor channel width of each stage, inductor structure and gate bias voltages. Also, the effect of inter-stage impedance on FoM was analyzed. And for noise simulation, accurate channel thermal noise model was used. Through these steps, FoM of 2-stage LNA was optimized. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Low noise amplifier / CMOS / Figure of merit / Inter-stage impedance / Noise figure / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 122, SDM2008-115, pp. 301-304, July 2008. | |
| Paper # | SDM2008-115 | |
| Date of Issue | 2008-07-02 (ED, SDM) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | ED2008-96 SDM2008-115 Link to ES Tech. Rep. Archives: ED2008-96 SDM2008-115 |
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| Conference Information | |
| Committee | SDM ED |
| Conference Date | 2008-07-09 - 2008-07-11 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kaderu２・７ |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | 2008 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices |
| Paper Information | |
| Registration To | SDM |
| Conference Code | 2008-07-SDM-ED |
| Language | English |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | 24 GHz Low Noise Amplifier Design in 65 nm CMOS Technology with Inter-Stage Matching Optimization |
| Sub Title (in English) | |
| Keyword(1) | Low noise amplifier |
| Keyword(2) | CMOS |
| Keyword(3) | Figure of merit |
| Keyword(4) | Inter-stage impedance |
| Keyword(5) | Noise figure |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Ickhyun Song |
| 1st Author's Affiliation | Seoul National University (Seoul National Univ.) |
| 2nd Author's Name | Hakchul Jung |
| 2nd Author's Affiliation | Seoul National University (Seoul National Univ.) |
| 3rd Author's Name | Hee-Sauk Jhon |
| 3rd Author's Affiliation | Seoul National University (Seoul National Univ.) |
| 4th Author's Name | Minsuk Koo |
| 4th Author's Affiliation | Seoul National University (Seoul National Univ.) |
| 5th Author's Name | Hyungcheol Shin |
| 5th Author's Affiliation | Seoul National University (Seoul National Univ.) |
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| Speaker | Author-1 |
| Date Time | 2008-07-11 15:05:00 |
| Presentation Time | 15 minutes |
| Registration for | SDM |
| Paper # | ED2008-96, SDM2008-115 |
| Volume (vol) | vol.108 |
| Number (no) | no.121(ED), no.122(SDM) |
| Page | pp.301-304 |
| #Pages | 4 |
| Date of Issue | 2008-07-02 (ED, SDM) |
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