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Paper Abstract and Keywords
Presentation 2008-07-11 11:35
A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology
Jae-Young Park, Jong-Kyu Song, Chang-Soo Jang, Joon-Tae Jang, San-Hong Kim, Sung-Ki Kim, Taek-Soo Kim (Dongbu HiTek) ED2008-76 SDM2008-95 Link to ES Tech. Rep. Archives: ED2008-76 SDM2008-95
Abstract (in Japanese) (See Japanese page) 
(in English) The holding voltage of the high-voltage devices the snapback breakdown condition has been known to be much smaller than the power supply voltage. Such characteristics cause the high-voltage ICs to be susceptible to the transient latch-up failure in the practical system applications, especially when these devices are used in the power-rail ESD clamp circuit. A new latchup-free design of the power-rail ESD clamp circuit with stacked-bipolar devices is proposed and successfully verified in a 0.35・ BCD (Bipolar-CMOS-DMOS) process to achieve the desired ESD level. The total holding voltage of the stacked-bipolar devices in the snapback breakdown condition can be larger than the power supply voltage.
Keyword (in Japanese) (See Japanese page) 
(in English) ESD (Electrostatic Discharge) / power-rail ESD clamp circuit / transient latch-up / stacked-bipolar devices / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 122, SDM2008-95, pp. 193-197, July 2008.
Paper # SDM2008-95 
Date of Issue 2008-07-02 (ED, SDM) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ED2008-76 SDM2008-95 Link to ES Tech. Rep. Archives: ED2008-76 SDM2008-95

Conference Information
Committee SDM ED  
Conference Date 2008-07-09 - 2008-07-11 
Place (in Japanese) (See Japanese page) 
Place (in English) Kaderu2・7 
Topics (in Japanese) (See Japanese page) 
Topics (in English) 2008 Asia-Pacific Workshop on Fundamentals and Applications of Advanced Semiconductor Devices 
Paper Information
Registration To SDM 
Conference Code 2008-07-SDM-ED 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Latchup-Free Power-Rail ESD Clamp Circuit with Stacked-Bipolar Devices in a High-Voltage Technology 
Sub Title (in English)  
Keyword(1) ESD (Electrostatic Discharge)  
Keyword(2) power-rail ESD clamp circuit  
Keyword(3) transient latch-up  
Keyword(4) stacked-bipolar devices  
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1st Author's Name Jae-Young Park  
1st Author's Affiliation Dongbu HiTek (Dongbu HiTek)
2nd Author's Name Jong-Kyu Song  
2nd Author's Affiliation Dongbu HiTek (Dongbu HiTek)
3rd Author's Name Chang-Soo Jang  
3rd Author's Affiliation Dongbu HiTek (Dongbu HiTek)
4th Author's Name Joon-Tae Jang  
4th Author's Affiliation Dongbu HiTek (Dongbu HiTek)
5th Author's Name San-Hong Kim  
5th Author's Affiliation Dongbu HiTek (Dongbu HiTek)
6th Author's Name Sung-Ki Kim  
6th Author's Affiliation Dongbu HiTek (Dongbu HiTek)
7th Author's Name Taek-Soo Kim  
7th Author's Affiliation Dongbu HiTek (Dongbu HiTek)
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Speaker Author-1 
Date Time 2008-07-11 11:35:00 
Presentation Time 15 minutes 
Registration for SDM 
Paper # ED2008-76, SDM2008-95 
Volume (vol) vol.108 
Number (no) no.121(ED), no.122(SDM) 
Page pp.193-197 
#Pages
Date of Issue 2008-07-02 (ED, SDM) 


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