| Paper Abstract and Keywords |
| Presentation |
2008-07-25 09:55
Architecture Optimization of a Group Signature Circuit
Sumio Morioka, Toshinori Araki, Toshiyuki Isshiki, Satoshi Obana, Kazue Sako, Isamu Teranishi (NEC) |
| Abstract |
(in Japanese) |
(See Japanese page) |
| (in English) |
Group signature scheme is one of the most active research area in recent cryptographic algorithms/applications. Typical signature algorithm is a combination of dozens of elliptic curve (EC), modular, integer and hash arithmetic operations on data whose bit width exceeds 1,000 bits. A full-H/W IP core is desired for the use of the group signature in SoCs in slow-clock mobile devices. In order to construct a high performance and configurable group signature IP, connecting multiple modular / EC arithmetic units (sub-IPs) and a simple controller not by a wide-band bus but by a narrow-band bus is appropriate. While conventional behavioral synthesis from C-language was used, the development of an additional behavioral synthesizer for parallel scheduling of sub-IP level (C function-library level) operations was necessary. We explored an optimum H/W architecture for a typical group signature algorithm
and found that at most 5 modular sub-IPs is enough. Practical H/W speed of less than 0.1 seconds at 100MHz on a 130nm standard cell ASIC library
was achieved. |
| Keyword |
(in Japanese) |
(See Japanese page) |
| (in English) |
Group signature / Security H/W / IP core architecture / Behavioral synthesis / C function level parallelism / / / |
| Reference Info. |
IEICE Tech. Rep., vol. 108, pp. 37-44, July 2008. |
| Paper # |
|
| Date of Issue |
2008-07-18 (ISEC) |
| ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
| Download PDF |
|
| Conference Information |
| Committee |
ISEC SITE IPSJ-CSEC |
| Conference Date |
2008-07-24 - 2008-07-25 |
| Place (in Japanese) |
(See Japanese page) |
| Place (in English) |
Fukuoka Institute of System LSI Design Industry |
| Topics (in Japanese) |
(See Japanese page) |
| Topics (in English) |
|
| Paper Information |
| Registration To |
IPSJ-CSEC |
| Conference Code |
2008-07-ISEC-SITE-CSEC |
| Language |
English (Japanese title is available) |
| Title (in Japanese) |
(See Japanese page) |
| Sub Title (in Japanese) |
(See Japanese page) |
| Title (in English) |
Architecture Optimization of a Group Signature Circuit |
| Sub Title (in English) |
|
| Keyword(1) |
Group signature |
| Keyword(2) |
Security H/W |
| Keyword(3) |
IP core architecture |
| Keyword(4) |
Behavioral synthesis |
| Keyword(5) |
C function level parallelism |
| Keyword(6) |
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| Keyword(7) |
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| Keyword(8) |
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| 1st Author's Name |
Sumio Morioka |
| 1st Author's Affiliation |
NEC Corporation (NEC) |
| 2nd Author's Name |
Toshinori Araki |
| 2nd Author's Affiliation |
NEC Corporation (NEC) |
| 3rd Author's Name |
Toshiyuki Isshiki |
| 3rd Author's Affiliation |
NEC Corporation (NEC) |
| 4th Author's Name |
Satoshi Obana |
| 4th Author's Affiliation |
NEC Corporation (NEC) |
| 5th Author's Name |
Kazue Sako |
| 5th Author's Affiliation |
NEC Corporation (NEC) |
| 6th Author's Name |
Isamu Teranishi |
| 6th Author's Affiliation |
NEC Corporation (NEC) |
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| Speaker |
Author-1 |
| Date Time |
2008-07-25 09:55:00 |
| Presentation Time |
25 minutes |
| Registration for |
IPSJ-CSEC |
| Paper # |
ISEC2008-40 |
| Volume (vol) |
vol.108 |
| Number (no) |
no.162 |
| Page |
pp.37-44 |
| #Pages |
8 |
| Date of Issue |
2008-07-18 (ISEC) |
|