Paper Abstract and Keywords |
Presentation |
2008-09-11 17:30
Consideration to Fast Simulation for Error Rate of Each Bit Position on LDPC Codes Yuto Matsunaga (Chuo Univ.), Manabu Hagiwara, Hideki Imai (Chuo Univ./AIST) IT2008-27 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
This paper, we consider fast simulation for error rate of each bit position on LDPC Codes.QC LDPC Codes has a theorem that error rate of each bit position are equal in invariable length.We propose a fast simulation's technique for error rate each bit position from this theorem.Running time of Simulation for Estimation for Error Rate of Each Bit Position on LDPC Codes takes two hours using our method. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
QC LDPC COdes / sum-product decoding / / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 202, IT2008-27, pp. 43-48, Sept. 2008. |
Paper # |
IT2008-27 |
Date of Issue |
2008-09-04 (IT) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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IT2008-27 |
Conference Information |
Committee |
IT |
Conference Date |
2008-09-11 - 2008-09-12 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Culture Resort Festone (Okinawa) |
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(See Japanese page) |
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Paper Information |
Registration To |
IT |
Conference Code |
2008-09-IT |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Consideration to Fast Simulation for Error Rate of Each Bit Position on LDPC Codes |
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Keyword(1) |
QC LDPC COdes |
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sum-product decoding |
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1st Author's Name |
Yuto Matsunaga |
1st Author's Affiliation |
Chuo University (Chuo Univ.) |
2nd Author's Name |
Manabu Hagiwara |
2nd Author's Affiliation |
Chuo University/National Institute of Advanced Industrial Science and Technology (Chuo Univ./AIST) |
3rd Author's Name |
Hideki Imai |
3rd Author's Affiliation |
Chuo University/National Institute of Advanced Industrial Science and Technology (Chuo Univ./AIST) |
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Speaker |
Author-1 |
Date Time |
2008-09-11 17:30:00 |
Presentation Time |
25 minutes |
Registration for |
IT |
Paper # |
IT2008-27 |
Volume (vol) |
vol.108 |
Number (no) |
no.202 |
Page |
pp.43-48 |
#Pages |
6 |
Date of Issue |
2008-09-04 (IT) |