Paper Abstract and Keywords |
Presentation |
2008-11-17 16:15
Soft Error Mitigation Techniques for FPGA Switch Matrices Yuki Kou, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (Nara Institute of Science and Technology) RECONF2008-45 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
Recentry, a soft error becomes a serious probrem as the process shrinking. Especially, SRAMs seriously suffer from a soft error, and thus various techniques have been proposed to deal with it. In this paper, we propose a technique to utilize ASRAM for the memory cells to control the pass transistors in an SRAM based FPGAs. We confirmed that the proposed techniques have high error tolerance than that of TMR when the ratio of 0's in the configuration bits are larger than some constant value. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Soft error / SRAM-based FPGA / Pass Transister / TMR / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 300, RECONF2008-45, pp. 39-44, Nov. 2008. |
Paper # |
RECONF2008-45 |
Date of Issue |
2008-11-10 (RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
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Download PDF |
RECONF2008-45 |