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Paper Abstract and Keywords
Presentation 2008-11-17 16:15
Soft Error Mitigation Techniques for FPGA Switch Matrices
Yuki Kou, Masaki Nakanishi, Shigeru Yamashita, Yasuhiko Nakashima (Nara Institute of Science and Technology) RECONF2008-45
Abstract (in Japanese) (See Japanese page) 
(in English) Recentry, a soft error becomes a serious probrem as the process shrinking. Especially, SRAMs seriously suffer from a soft error, and thus various techniques have been proposed to deal with it. In this paper, we propose a technique to utilize ASRAM for the memory cells to control the pass transistors in an SRAM based FPGAs. We confirmed that the proposed techniques have high error tolerance than that of TMR when the ratio of 0's in the configuration bits are larger than some constant value.
Keyword (in Japanese) (See Japanese page) 
(in English) Soft error / SRAM-based FPGA / Pass Transister / TMR / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 300, RECONF2008-45, pp. 39-44, Nov. 2008.
Paper # RECONF2008-45 
Date of Issue 2008-11-10 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF RECONF2008-45

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2008-11-17 - 2008-11-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu Science and Research Park 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2008 ―New field of VLSI design― 
Paper Information
Registration To RECONF 
Conference Code 2008-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Soft Error Mitigation Techniques for FPGA Switch Matrices 
Sub Title (in English)  
Keyword(1) Soft error  
Keyword(2) SRAM-based FPGA  
Keyword(3) Pass Transister  
Keyword(4) TMR  
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1st Author's Name Yuki Kou  
1st Author's Affiliation Nara Institute of Science and Technology (Nara Institute of Science and Technology)
2nd Author's Name Masaki Nakanishi  
2nd Author's Affiliation Nara Institute of Science and Technology (Nara Institute of Science and Technology)
3rd Author's Name Shigeru Yamashita  
3rd Author's Affiliation Nara Institute of Science and Technology (Nara Institute of Science and Technology)
4th Author's Name Yasuhiko Nakashima  
4th Author's Affiliation Nara Institute of Science and Technology (Nara Institute of Science and Technology)
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Speaker Author-1 
Date Time 2008-11-17 16:15:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2008-45 
Volume (vol) vol.108 
Number (no) no.300 
Page pp.39-44 
#Pages
Date of Issue 2008-11-10 (RECONF) 


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