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Paper Abstract and Keywords
Presentation 2008-11-17 15:00
A Study of Local Interconnect Architecture for Variable Grain Logic Cell
Kazuki Inoue, Motoki Amagasaki, Masahiro Iida, Toshinori Sueyoshi (Kumamoto Univ.) RECONF2008-42
Abstract (in Japanese) (See Japanese page) 
(in English) Reconfigurable logic devices (RLDs) are classified as fine-grained or coarse-grained types on the basis of their basic logic cell architecture. In general, each architecture has its own advantages; therefore, it is difficult to achieve a balance between the operation speed and implementation area in various applications. In this study, we propose a variable grain logic cell (VGLC) architecture. Its key feature is the variable granularity that is a trade-off between the coarse-grained and fine-grained types required for the implementation arithmetic and random logic, respectively. In this paper, we propose local interconnect structure, which is a corssbar switching circuit, for the VGLC. In order to discuss the trade-off between circuit resources and flexibility, we proposed some types of structure, and evaluated them. As a result, we found that the low-flexibility local interconnect has same effects compared to high-flexbility one.
Keyword (in Japanese) (See Japanese page) 
(in English) reconfigurable logic device / coarse-grain / fine-grain / local interconnect / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 300, RECONF2008-42, pp. 21-26, Nov. 2008.
Paper # RECONF2008-42 
Date of Issue 2008-11-10 (RECONF) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2008-11-17 - 2008-11-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu Science and Research Park 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2008 ―New field of VLSI design― 
Paper Information
Registration To RECONF 
Conference Code 2008-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Study of Local Interconnect Architecture for Variable Grain Logic Cell 
Sub Title (in English)  
Keyword(1) reconfigurable logic device  
Keyword(2) coarse-grain  
Keyword(3) fine-grain  
Keyword(4) local interconnect  
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1st Author's Name Kazuki Inoue  
1st Author's Affiliation Kumamoto University (Kumamoto Univ.)
2nd Author's Name Motoki Amagasaki  
2nd Author's Affiliation Kumamoto University (Kumamoto Univ.)
3rd Author's Name Masahiro Iida  
3rd Author's Affiliation Kumamoto University (Kumamoto Univ.)
4th Author's Name Toshinori Sueyoshi  
4th Author's Affiliation Kumamoto University (Kumamoto Univ.)
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Speaker Author-1 
Date Time 2008-11-17 15:00:00 
Presentation Time 25 minutes 
Registration for RECONF 
Paper # RECONF2008-42 
Volume (vol) vol.108 
Number (no) no.300 
Page pp.21-26 
#Pages
Date of Issue 2008-11-10 (RECONF) 


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