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Paper Abstract and Keywords
Presentation 2008-11-18 10:30
A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems
Nobuaki Tojo, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.) VLD2008-76 DC2008-44
Abstract (in Japanese) (See Japanese page) 
(in English) In an embedded system where a single application or a class of applications are repeatedly executed on a processor, its memory configuration can be customized such that an optimal one is achieved.
We can have an optimal two-level cache and scratch pad memory configuration which minimizes overall memory access time or energy consumption by varying the seven parameters: the number of sets of an L1/L2 cache, a line size of an L1/L2 cache, an associativity of an L1/L2 cache, and a size of a scratch pad memory.
In this paper, we propose two-level cache and scratch pad memory design space exploration algorithms: CRCB-T and CRCB-S.
Our proposed approach totally runs a maximum of 3172.94 faster compared to the conventional exhaustive approach.
Keyword (in Japanese) (See Japanese page) 
(in English) cache / two-level cache / scratch pad memory / cache simulation / cache optimization / embedded system / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 298, VLD2008-76, pp. 97-102, Nov. 2008.
Paper # VLD2008-76 
Date of Issue 2008-11-10 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2008-76 DC2008-44

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2008-11-17 - 2008-11-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu Science and Research Park 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2008 ―New field of VLSI design― 
Paper Information
Registration To VLD 
Conference Code 2008-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Two-level Cache and Scratch Pad Memory Simulation for Embedded Systems 
Sub Title (in English)  
Keyword(1) cache  
Keyword(2) two-level cache  
Keyword(3) scratch pad memory  
Keyword(4) cache simulation  
Keyword(5) cache optimization  
Keyword(6) embedded system  
Keyword(7)  
Keyword(8)  
1st Author's Name Nobuaki Tojo  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Nozomu Togawa  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Masao Yanagisawa  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Tatsuo Ohtsuki  
4th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2008-11-18 10:30:00 
Presentation Time 25 minutes 
Registration for VLD 
Paper # VLD2008-76, DC2008-44 
Volume (vol) vol.108 
Number (no) no.298(VLD), no.299(DC) 
Page pp.97-102 
#Pages
Date of Issue 2008-11-10 (VLD, DC) 


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