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Paper Abstract and Keywords
Presentation 2008-11-19 10:50
A Fast Simulation Technique of Processor Power Supply Noise using Capacitance Charging Model
Fukuichi Iwasa, Takuya Sawada, Mitsuya Fukazawa, Makoto Nagata (Kobe Univ.) CPM2008-94 ICD2008-93 Link to ES Tech. Rep. Archives: CPM2008-94 ICD2008-93
Abstract (in Japanese) (See Japanese page) 
(in English) A fast simulation technique is proposed for the power supply noise analysis of the large-scale digital processor. The analysis cost is improved by reducing the scale of capacitance charging model with capacitance statistics data. The proposed technique is applied to a test chip fabricated with a 90nm CMOS process technology and shortens analysis time 62.8 % at the maximum at the maintained precision.
Keyword (in Japanese) (See Japanese page) 
(in English) Power supply noise / Capacitance charging model / SRAM model / Noise analysis / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, no. 302, ICD2008-93, pp. 31-36, Nov. 2008.
Paper # ICD2008-93 
Date of Issue 2008-11-11 (CPM, ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
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All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF CPM2008-94 ICD2008-93 Link to ES Tech. Rep. Archives: CPM2008-94 ICD2008-93

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2008-11-17 - 2008-11-19 
Place (in Japanese) (See Japanese page) 
Place (in English) Kitakyushu Science and Research Park 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2008 ―New field of VLSI design― 
Paper Information
Registration To ICD 
Conference Code 2008-11-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Fast Simulation Technique of Processor Power Supply Noise using Capacitance Charging Model 
Sub Title (in English)  
Keyword(1) Power supply noise  
Keyword(2) Capacitance charging model  
Keyword(3) SRAM model  
Keyword(4) Noise analysis  
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1st Author's Name Fukuichi Iwasa  
1st Author's Affiliation Kobe University (Kobe Univ.)
2nd Author's Name Takuya Sawada  
2nd Author's Affiliation Kobe University (Kobe Univ.)
3rd Author's Name Mitsuya Fukazawa  
3rd Author's Affiliation Kobe University (Kobe Univ.)
4th Author's Name Makoto Nagata  
4th Author's Affiliation Kobe University (Kobe Univ.)
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Speaker Author-1 
Date Time 2008-11-19 10:50:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # CPM2008-94, ICD2008-93 
Volume (vol) vol.108 
Number (no) no.301(CPM), no.302(ICD) 
Page pp.31-36 
#Pages
Date of Issue 2008-11-11 (CPM, ICD) 


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