Paper Abstract and Keywords |
Presentation |
2008-12-12 13:45
Improvement of Logic Element used in Via programmable logic device VPEX Tomohiro Nishimoto, Masahide Kawarasaki, Eiji Hasegawa, Tomohiro Terakawa, Takeshi Fujino (Ritsumei Univ) ICD2008-122 Link to ES Tech. Rep. Archives: ICD2008-122 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
We have been studied the via-programmable device (Via Programmable logic using EXclusive or array) whose logic element consist of the combination of complex-gate-type EXOR gate and Inverter. 12 kinds of logic functions including all two-input and one-output functions can be programmed by changing via-1 layout. Various kinds of combination logics are configured by changing via-3 layout which controls the connection between LEs. D-Flipflops (DFFs) can be realized by using 4 LEs, so sequential-logic is also programmed in the VPEX LE array. In this study, we improved the elements of LE and DFFs can be realized by using only 2 LEs without increasing area of each LE. The chip-area of the DFFs-rich circuits are decreased by 20 % due to this improvement. Furthermore, the gate delay of LE is decreased by optimizing transistor size. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Via-programmable logic / EB direct writing / Exclusive-OR / structured ASIC / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 347, ICD2008-122, pp. 101-106, Dec. 2008. |
Paper # |
ICD2008-122 |
Date of Issue |
2008-12-04 (ICD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
ICD2008-122 Link to ES Tech. Rep. Archives: ICD2008-122 |
Conference Information |
Committee |
ICD |
Conference Date |
2008-12-11 - 2008-12-12 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
Tokyo Inst. Tech., Ohokayama Campus, Kokusa-Kouryu-Kaikan |
Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Workshop for Graduate Student and Young Researchers |
Paper Information |
Registration To |
ICD |
Conference Code |
2008-12-ICD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Improvement of Logic Element used in Via programmable logic device VPEX |
Sub Title (in English) |
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Keyword(1) |
Via-programmable logic |
Keyword(2) |
EB direct writing |
Keyword(3) |
Exclusive-OR |
Keyword(4) |
structured ASIC |
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1st Author's Name |
Tomohiro Nishimoto |
1st Author's Affiliation |
Ritsumeikan University (Ritsumei Univ) |
2nd Author's Name |
Masahide Kawarasaki |
2nd Author's Affiliation |
Ritsumeikan University (Ritsumei Univ) |
3rd Author's Name |
Eiji Hasegawa |
3rd Author's Affiliation |
Ritsumeikan University (Ritsumei Univ) |
4th Author's Name |
Tomohiro Terakawa |
4th Author's Affiliation |
Ritsumeikan University (Ritsumei Univ) |
5th Author's Name |
Takeshi Fujino |
5th Author's Affiliation |
Ritsumeikan University (Ritsumei Univ) |
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Speaker |
Author-1 |
Date Time |
2008-12-12 13:45:00 |
Presentation Time |
25 minutes |
Registration for |
ICD |
Paper # |
ICD2008-122 |
Volume (vol) |
vol.108 |
Number (no) |
no.347 |
Page |
pp.101-106 |
#Pages |
6 |
Date of Issue |
2008-12-04 (ICD) |
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