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| Presentation | 2009-01-14 14:45 A Power Saving Scheme on Multicore Processors Using OSCAR API Ryo Nakagawa, Masayoshi Mase, Jun Shirako, Keiji Kimura, Hironori Kasahara (Waseda Univ.) Link to ES Tech. Rep. Archives:  ICD2008-145 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | Effective power reduction of an application program on multicore processors requires appropriate power control for each on-chip resource by compilers or users. These low power techniques need an application program interface (API) to realize power control in a user program. This paper proposes a power saving scheme for multicore processors using OSCAR API developed in NEDO “Multicore for Realtime Consumer Electronics” project. The proposed scheme has been implemented in OSCAR compiler to realize the power reduction for fastest execution mode, which minimizes power consumption without performance degradation, and the realtime execution mode to minimize power consumption under realtime constrains. The proposed scheme is evaluated on an 8 cores SH4A multicore processor RP2, newly developed for consumer electronics by Renesas Technology Corp., Hitachi, Ltd. and Waseda University in the above project. For the fastest execution mode, consumed energy was reduced by 13.05% for SPEC2000 art and 3.99% for SPEC2000 equake. Also, for the realtime execution mode, consumed power was reduced by 87.9% for AAC encoder and 73.2% for MPEG2 decoder. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Multicore Processor / Low Power / Parallelizing Compiler / API / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, pp. 93-98, Jan. 2009. | |
| Paper # | ||
| Date of Issue | 2009-01-06 (ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | Link to ES Tech. Rep. Archives: ICD2008-145 |
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| Conference Information | |
| Committee | ICD IPSJ-ARC IPSJ-EMB |
| Conference Date | 2009-01-13 - 2009-01-14 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Shoushin Kaikan |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Embedded System Platform |
| Paper Information | |
| Registration To | IPSJ-ARC |
| Conference Code | 2009-01-ICD-ARC-EMB |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Power Saving Scheme on Multicore Processors Using OSCAR API |
| Sub Title (in English) | |
| Keyword(1) | Multicore Processor |
| Keyword(2) | Low Power |
| Keyword(3) | Parallelizing Compiler |
| Keyword(4) | API |
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| Keyword(6) | |
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| 1st Author's Name | Ryo Nakagawa |
| 1st Author's Affiliation | Waseda University (Waseda Univ.) |
| 2nd Author's Name | Masayoshi Mase |
| 2nd Author's Affiliation | Waseda University (Waseda Univ.) |
| 3rd Author's Name | Jun Shirako |
| 3rd Author's Affiliation | Waseda University (Waseda Univ.) |
| 4th Author's Name | Keiji Kimura |
| 4th Author's Affiliation | Waseda University (Waseda Univ.) |
| 5th Author's Name | Hironori Kasahara |
| 5th Author's Affiliation | Waseda University (Waseda Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-01-14 14:45:00 |
| Presentation Time | 30 minutes |
| Registration for | IPSJ-ARC |
| Paper # | ICD2008-145 |
| Volume (vol) | vol.108 |
| Number (no) | no.375 |
| Page | pp.93-98 |
| #Pages | 6 |
| Date of Issue | 2009-01-06 (ICD) |
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