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Paper Abstract and Keywords
Presentation 2009-01-14 11:15
Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications
Teruo Kamiyama, Yasutaka Wada, Akihiro Hayashi, Masayoshi Mase, Hirofumi Nakano, Takeshi Watanabe, Keiji Kimura, Hironori Kasahara (Waseda Univ.) Link to ES Tech. Rep. Archives: ICD2008-140
Abstract (in Japanese) (See Japanese page) 
(in English) This paper describes a heterogeneous multicore architecture having accelerator cores in addition to general purpose cores, an automatic parallelizing compiler that cooperatively works with the heterogeneous multicore, a heterogeneous multicore architecture simulation environment, and performance evaluation results with the simulation environment. For the performance evaluation, multimedia applications written in C or Fortran, considered with parallelization by the compiler, are used. As a result, the evaluated heterogeneous multicore having two general purpose cores and two accelerator cores achieves 9.82 times speedup from MP3 encoder. This architecture also achieves 14.64 times speedup from JPEG2000 encoder.
Keyword (in Japanese) (See Japanese page) 
(in English) Heterogeneous multicore / OSCAR Compiler / / / / / /  
Reference Info. IEICE Tech. Rep., vol. 108, pp. 63-68, Jan. 2009.
Paper #  
Date of Issue 2009-01-06 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF Link to ES Tech. Rep. Archives: ICD2008-140

Conference Information
Committee ICD IPSJ-ARC IPSJ-EMB  
Conference Date 2009-01-13 - 2009-01-14 
Place (in Japanese) (See Japanese page) 
Place (in English) Shoushin Kaikan 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Embedded System Platform 
Paper Information
Registration To IPSJ-ARC 
Conference Code 2009-01-ICD-ARC-EMB 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Performance Evaluation of Parallelizing Compiler Cooperated Heterogeneous Multicore Architecture Using Media Applications 
Sub Title (in English)  
Keyword(1) Heterogeneous multicore  
Keyword(2) OSCAR Compiler  
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1st Author's Name Teruo Kamiyama  
1st Author's Affiliation Waseda University (Waseda Univ.)
2nd Author's Name Yasutaka Wada  
2nd Author's Affiliation Waseda University (Waseda Univ.)
3rd Author's Name Akihiro Hayashi  
3rd Author's Affiliation Waseda University (Waseda Univ.)
4th Author's Name Masayoshi Mase  
4th Author's Affiliation Waseda University (Waseda Univ.)
5th Author's Name Hirofumi Nakano  
5th Author's Affiliation Waseda University (Waseda Univ.)
6th Author's Name Takeshi Watanabe  
6th Author's Affiliation Waseda University (Waseda Univ.)
7th Author's Name Keiji Kimura  
7th Author's Affiliation Waseda University (Waseda Univ.)
8th Author's Name Hironori Kasahara  
8th Author's Affiliation Waseda University (Waseda Univ.)
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Speaker Author-1 
Date Time 2009-01-14 11:15:00 
Presentation Time 30 minutes 
Registration for IPSJ-ARC 
Paper # ICD2008-140 
Volume (vol) vol.108 
Number (no) no.375 
Page pp.63-68 
#Pages
Date of Issue 2009-01-06 (ICD) 


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