Paper Abstract and Keywords |
Presentation |
2009-01-30 12:20
A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems Harunobu Yoshida, Nozomu Togawa, Masao Yanagisawa, Tatsuo Ohtsuki (Waseda Univ.), Masayoshi Tachibana (KUT) VLD2008-115 CPSY2008-77 RECONF2008-79 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In this paper, we propose an on-chip bus optimization algorithm for a multi-layer bus architecture. Our algorithm efficiently searches for an optimal selection of the number and bit-size of buses, CPU-bus connection topology, and the priority of each CPU subject to the time constraint for given embedded applications. It is necessary to estimate the running time of applications with taking into consideration the effect of memory access conflict. Before taking into consideration the effect of memory access conflict, our approach removes configurations which violate the constraints. By reducing the design space in this way we can obtain an optimal configuration in shorter time. Our algorithm is 8.55 faster compared to the exhaustive approach. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
MPSoC / Bus Architecture Optimization / Embedded System / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 412, VLD2008-115, pp. 141-146, Jan. 2009. |
Paper # |
VLD2008-115 |
Date of Issue |
2009-01-22 (VLD, CPSY, RECONF) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
Download PDF |
VLD2008-115 CPSY2008-77 RECONF2008-79 |
Conference Information |
Committee |
VLD CPSY RECONF IPSJ-SLDM |
Conference Date |
2009-01-29 - 2009-01-30 |
Place (in Japanese) |
(See Japanese page) |
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(See Japanese page) |
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Paper Information |
Registration To |
VLD |
Conference Code |
2009-01-VLD-CPSY-RECONF-SLDM |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
A Multi-layer Bus Architecture Optimization Algorithm for MPSoC in Embedded Systems |
Sub Title (in English) |
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Keyword(1) |
MPSoC |
Keyword(2) |
Bus Architecture Optimization |
Keyword(3) |
Embedded System |
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1st Author's Name |
Harunobu Yoshida |
1st Author's Affiliation |
Waseda University (Waseda Univ.) |
2nd Author's Name |
Nozomu Togawa |
2nd Author's Affiliation |
Waseda University (Waseda Univ.) |
3rd Author's Name |
Masao Yanagisawa |
3rd Author's Affiliation |
Waseda University (Waseda Univ.) |
4th Author's Name |
Tatsuo Ohtsuki |
4th Author's Affiliation |
Waseda University (Waseda Univ.) |
5th Author's Name |
Masayoshi Tachibana |
5th Author's Affiliation |
Kochi University of Technology (KUT) |
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Speaker |
Author-1 |
Date Time |
2009-01-30 12:20:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2008-115, CPSY2008-77, RECONF2008-79 |
Volume (vol) |
vol.108 |
Number (no) |
no.412(VLD), no.413(CPSY), no.414(RECONF) |
Page |
pp.141-146 |
#Pages |
6 |
Date of Issue |
2009-01-22 (VLD, CPSY, RECONF) |
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