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| Paper Abstract and Keywords | ||
| Presentation | 2009-03-05 15:45 Single-Cycle-Accessible Two-Level Cache Architecture Seiichiro Yamaguchi, Tohru Ishihara, Hiroto Yasuura (Kyushu Univ.)  CPSY2008-91 DC2008-82 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | A small L0-cache located between an MPU core and an L1-cache is widely used in embedded processors for reducing the energy consumption of memory subsystems. Since the L0-cache is small, if there is a hit, the energy consumption will be reduced. On the other hand, if there is a miss, at least one extra cycle is needed to access the L1-cache. This degrades the processor performance. Single-cycle-accessible Two-level Cache (STC) architecture proposed in this paper can resolve the problem in the conventional L0-cache based approach. Both a small L0 and a large L1 caches in our STC architecture can be accessed from an MPU core within a single cycle. A compilation technique for e®ectively utilizing the STC architecture is also presented in this paper. Experiments using several benchmark programs demonstrate that our approach reduces the energy consumption of memory subsystems by 64% in the best case and by 41% on an average without any performance degradation compared to the conventional L0-cache based approach. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | Embedded system / Cache memory / Energy consumption / / / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 108, no. 464, DC2008-82, pp. 19-24, March 2009. | |
| Paper # | DC2008-82 | |
| Date of Issue | 2009-02-26 (CPSY, DC) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPSY2008-91 DC2008-82 |
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| Conference Information | |
| Committee | DC CPSY IPSJ-SLDM IPSJ-EMB |
| Conference Date | 2009-03-05 - 2009-03-06 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Sado Island Integrated Development Center |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | ETNET2009 |
| Paper Information | |
| Registration To | DC |
| Conference Code | 2009-03-DC |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Single-Cycle-Accessible Two-Level Cache Architecture |
| Sub Title (in English) | |
| Keyword(1) | Embedded system |
| Keyword(2) | Cache memory |
| Keyword(3) | Energy consumption |
| Keyword(4) | |
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| 1st Author's Name | Seiichiro Yamaguchi |
| 1st Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 2nd Author's Name | Tohru Ishihara |
| 2nd Author's Affiliation | Kyushu University (Kyushu Univ.) |
| 3rd Author's Name | Hiroto Yasuura |
| 3rd Author's Affiliation | Kyushu University (Kyushu Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-03-05 15:45:00 |
| Presentation Time | 30 minutes |
| Registration for | DC |
| Paper # | CPSY2008-91, DC2008-82 |
| Volume (vol) | vol.108 |
| Number (no) | no.463(CPSY), no.464(DC) |
| Page | pp.19-24 |
| #Pages | 6 |
| Date of Issue | 2009-02-26 (CPSY, DC) |
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