Paper Abstract and Keywords |
Presentation |
2009-03-12 14:15
Automatic generation of Network-on-Chip topology under link length and latency constraint Hideo Tanida (Univ. of Tokyo), Hiroaki Yoshida (Univ. of Tokyo/JST-CREST), Takeshi Matsumoto (Univ. of Tokyo), Masahiro Fujita (Univ. of Tokyo/JST-CREST) VLD2008-148 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
With wire delay becoming dominant compared to transistor delay in deep-submicron era, the performance of SoC is more affected by interconnect. Although many NoC (Network-on-Chip) architectures which improve interconnect performance are proposed, automatically finding the most efficient one for a given application and mapping the function blocks onto it, is still an open issue. This paper proposes a method for generating a custom NoC which meets communication link-length and latency requirements. Additional constraint for floor-planning and interconnect architecture generation, to existing integer-linear-programming-based approach, enables link-length and latency requirement to be met in the generated NoC architecture. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Network-on-Chip / linear programming / guaranteed performance / floor planning / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 108, no. 478, VLD2008-148, pp. 129-134, March 2009. |
Paper # |
VLD2008-148 |
Date of Issue |
2009-03-04 (VLD) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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VLD2008-148 |
Conference Information |
Committee |
VLD |
Conference Date |
2009-03-11 - 2009-03-13 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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Topics (in Japanese) |
(See Japanese page) |
Topics (in English) |
Design Technology for a System-on-Silicon |
Paper Information |
Registration To |
VLD |
Conference Code |
2009-03-VLD |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Automatic generation of Network-on-Chip topology under link length and latency constraint |
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Keyword(1) |
Network-on-Chip |
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linear programming |
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guaranteed performance |
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floor planning |
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1st Author's Name |
Hideo Tanida |
1st Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
2nd Author's Name |
Hiroaki Yoshida |
2nd Author's Affiliation |
The University of Tokyo/JST-CREST (Univ. of Tokyo/JST-CREST) |
3rd Author's Name |
Takeshi Matsumoto |
3rd Author's Affiliation |
The University of Tokyo (Univ. of Tokyo) |
4th Author's Name |
Masahiro Fujita |
4th Author's Affiliation |
The University of Tokyo/JST-CREST (Univ. of Tokyo/JST-CREST) |
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Speaker |
Author-1 |
Date Time |
2009-03-12 14:15:00 |
Presentation Time |
25 minutes |
Registration for |
VLD |
Paper # |
VLD2008-148 |
Volume (vol) |
vol.108 |
Number (no) |
no.478 |
Page |
pp.129-134 |
#Pages |
6 |
Date of Issue |
2009-03-04 (VLD) |
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