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Paper Abstract and Keywords
Presentation 2009-05-25 10:30
An Implementation of Artificial Neural Network on FPGA by VHDL -- Design Pattern Recognition Device --
Tadatoshi Nagao, Ikutarou Mizukami, Tatsuya Honda, Tomohiro Fujita, Minoru Motoki, Kazunori Matsuo, Hidenori Ohyama (Kumamoto National Coll. of Tech.), Hiroyasu Yamamoto, Norihiro Kurokawa (techno design) NC2009-1
Abstract (in Japanese) (See Japanese page) 
(in English) On software, Neural Network can't show its true ability. So, we try speedup it by hardware. At this time, we studied about how to hardware Neural Network. To realize Neural Network on digital method, we've contrived to decline its circuit scale. We verified behavior of the Neural Network which has pattern recognition ability, and we showed that it has generalization ability.
Keyword (in Japanese) (See Japanese page) 
(in English) digital neuro device / pattern recognition / FPGA / / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 53, NC2009-1, pp. 1-6, May 2009.
Paper # NC2009-1 
Date of Issue 2009-05-18 (NC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
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Conference Information
Committee NC  
Conference Date 2009-05-25 - 2009-05-26 
Place (in Japanese) (See Japanese page) 
Place (in English) OIST, Okinawa 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Machine Learning Approach to Biodata Mining in Biological Phenomena, and General 
Paper Information
Registration To NC 
Conference Code 2009-05-NC 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) An Implementation of Artificial Neural Network on FPGA by VHDL 
Sub Title (in English) Design Pattern Recognition Device 
Keyword(1) digital neuro device  
Keyword(2) pattern recognition  
Keyword(3) FPGA  
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1st Author's Name Tadatoshi Nagao  
1st Author's Affiliation Kumamoto National College of Technology (Kumamoto National Coll. of Tech.)
2nd Author's Name Ikutarou Mizukami  
2nd Author's Affiliation Kumamoto National College of Technology (Kumamoto National Coll. of Tech.)
3rd Author's Name Tatsuya Honda  
3rd Author's Affiliation Kumamoto National College of Technology (Kumamoto National Coll. of Tech.)
4th Author's Name Tomohiro Fujita  
4th Author's Affiliation Kumamoto National College of Technology (Kumamoto National Coll. of Tech.)
5th Author's Name Minoru Motoki  
5th Author's Affiliation Kumamoto National College of Technology (Kumamoto National Coll. of Tech.)
6th Author's Name Kazunori Matsuo  
6th Author's Affiliation Kumamoto National College of Technology (Kumamoto National Coll. of Tech.)
7th Author's Name Hidenori Ohyama  
7th Author's Affiliation Kumamoto National College of Technology (Kumamoto National Coll. of Tech.)
8th Author's Name Hiroyasu Yamamoto  
8th Author's Affiliation Techno Design Corporation (techno design)
9th Author's Name Norihiro Kurokawa  
9th Author's Affiliation Techno Design Corporation (techno design)
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Speaker Author-1 
Date Time 2009-05-25 10:30:00 
Presentation Time 30 minutes 
Registration for NC 
Paper # NC2009-1 
Volume (vol) vol.109 
Number (no) no.53 
Page pp.1-6 
#Pages
Date of Issue 2009-05-18 (NC) 


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