Paper Abstract and Keywords |
Presentation |
2009-05-25 10:30
An Implementation of Artificial Neural Network on FPGA by VHDL
-- Design Pattern Recognition Device -- Tadatoshi Nagao, Ikutarou Mizukami, Tatsuya Honda, Tomohiro Fujita, Minoru Motoki, Kazunori Matsuo, Hidenori Ohyama (Kumamoto National Coll. of Tech.), Hiroyasu Yamamoto, Norihiro Kurokawa (techno design) NC2009-1 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
On software, Neural Network can't show its true ability. So, we try speedup it by hardware. At this time, we studied about how to hardware Neural Network. To realize Neural Network on digital method, we've contrived to decline its circuit scale. We verified behavior of the Neural Network which has pattern recognition ability, and we showed that it has generalization ability. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
digital neuro device / pattern recognition / FPGA / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 53, NC2009-1, pp. 1-6, May 2009. |
Paper # |
NC2009-1 |
Date of Issue |
2009-05-18 (NC) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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NC2009-1 |
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