Paper Abstract and Keywords |
Presentation |
2009-08-04 18:00
Acceleration of Monte-Carlo Go by FPGA-based Hardware Kenichi Koizumi (Univ. of Tokyo), Yasuo Ishii (NEC Corp.), Kazuki Yoshizoe (JST), Takefumi Miyoshi (Tokyo Inst. of Tech.), Yutaka Sugawara (IBM), Mary Inaba, Kei Hiraki (Univ. of Tokyo) CPSY2009-19 |
Abstract |
(in Japanese) |
(See Japanese page) |
(in English) |
In the monte-carlo simulation of Go, it takes time to run playouts. There were attempts of accelerating
by implementing circuits for playout on FPGA, but it is difficult to realize high-speed playouts because of
high utilization of resources in a FPGA. In this paper, we propose an algorithm, Triple Line-based Playout for Go
(TLPG) to accelerate playouts for the monte-carlo tree search for computer-go game. We implemented the playout
logics on FPGA for 9 x 9 and 19 x 19 boards. With the optimizations, We achieved 13104playouts/sec in 9 x 9
and 2055playouts/sec in 19 x 19 board in simulation. By making games with GNU Go on a host Computer, We
evaluation the playouts of TLPG. |
Keyword |
(in Japanese) |
(See Japanese page) |
(in English) |
Go / Monte-carlo tree search / FPGA / / / / / |
Reference Info. |
IEICE Tech. Rep., vol. 109, no. 168, CPSY2009-19, pp. 55-60, Aug. 2009. |
Paper # |
CPSY2009-19 |
Date of Issue |
2009-07-28 (CPSY) |
ISSN |
Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 |
Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) |
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CPSY2009-19 |
Conference Information |
Committee |
CPSY DC |
Conference Date |
2009-08-04 - 2009-08-05 |
Place (in Japanese) |
(See Japanese page) |
Place (in English) |
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Topics (in Japanese) |
(See Japanese page) |
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Paper Information |
Registration To |
CPSY |
Conference Code |
2009-08-CPSY-DC |
Language |
Japanese |
Title (in Japanese) |
(See Japanese page) |
Sub Title (in Japanese) |
(See Japanese page) |
Title (in English) |
Acceleration of Monte-Carlo Go by FPGA-based Hardware |
Sub Title (in English) |
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Keyword(1) |
Go |
Keyword(2) |
Monte-carlo tree search |
Keyword(3) |
FPGA |
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1st Author's Name |
Kenichi Koizumi |
1st Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
2nd Author's Name |
Yasuo Ishii |
2nd Author's Affiliation |
NEC Corporation (NEC Corp.) |
3rd Author's Name |
Kazuki Yoshizoe |
3rd Author's Affiliation |
Japan Science and Technology Agency (JST) |
4th Author's Name |
Takefumi Miyoshi |
4th Author's Affiliation |
Tokyo Institute of Thechnology (Tokyo Inst. of Tech.) |
5th Author's Name |
Yutaka Sugawara |
5th Author's Affiliation |
IBM Thomas J. Watson Research Center (IBM) |
6th Author's Name |
Mary Inaba |
6th Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
7th Author's Name |
Kei Hiraki |
7th Author's Affiliation |
University of Tokyo (Univ. of Tokyo) |
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Speaker |
Author-1 |
Date Time |
2009-08-04 18:00:00 |
Presentation Time |
30 minutes |
Registration for |
CPSY |
Paper # |
CPSY2009-19 |
Volume (vol) |
vol.109 |
Number (no) |
no.168 |
Page |
pp.55-60 |
#Pages |
6 |
Date of Issue |
2009-07-28 (CPSY) |
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