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Paper Abstract and Keywords
Presentation 2009-10-02 10:00
Thermal Noise Effects Caused by Settling Time Optimization in Switched-Capacitor Circuits
Dong Ta Ngoc Huy, Masaya Miyahara, Akira Matsuzawa (Tokyo Inst. of Tech.) ICD2009-48 Link to ES Tech. Rep. Archives: ICD2009-48
Abstract (in Japanese) (See Japanese page) 
(in English) Switch thermal noise represents a major limitation on the performance of switched-capacitor circuits. In these circuits, the total noise power can be reduced by increasing the sampling capacitance of the circuits. However, it also increases the settling time, hence requires high-performance opamps. This leads to larger power dissipation. A pole-zero cancellation method can be used to improve the settling time while maintaining the power consumption. This paper describes the noise effects caused by this settling time optimization technique in switched-capacitor amplifiers. Theory and simulation results show that the pole-zero cancellation is highly power-efficient technique, even though it increases the noise power.
Keyword (in Japanese) (See Japanese page) 
(in English) switched-capacitor circuits / switch on-resistance / thermal noise / / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 214, ICD2009-48, pp. 81-86, Oct. 2009.
Paper # ICD2009-48 
Date of Issue 2009-09-24 (ICD) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
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reproduction
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF ICD2009-48 Link to ES Tech. Rep. Archives: ICD2009-48

Conference Information
Committee ICD ITE-IST  
Conference Date 2009-10-01 - 2009-10-02 
Place (in Japanese) (See Japanese page) 
Place (in English) CIC Tokyo (Tamachi) 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Analog, Mixed analog and digital, RF, and sensor interface circuitry 
Paper Information
Registration To ICD 
Conference Code 2009-10-ICD-IST 
Language English 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) Thermal Noise Effects Caused by Settling Time Optimization in Switched-Capacitor Circuits 
Sub Title (in English)  
Keyword(1) switched-capacitor circuits  
Keyword(2) switch on-resistance  
Keyword(3) thermal noise  
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1st Author's Name Dong Ta Ngoc Huy  
1st Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
2nd Author's Name Masaya Miyahara  
2nd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
3rd Author's Name Akira Matsuzawa  
3rd Author's Affiliation Tokyo Institute of Technology (Tokyo Inst. of Tech.)
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Date Time 2009-10-02 10:00:00 
Presentation Time 25 minutes 
Registration for ICD 
Paper # ICD2009-48 
Volume (vol) vol.109 
Number (no) no.214 
Page pp.81-86 
#Pages
Date of Issue 2009-09-24 (ICD) 


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