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| Presentation | 2009-12-02 13:50 [Invited Talk] Failures due to Terrestriall Neutrons in Most Advanced Semicondutor Devices -- Impacts and Hardening Techniques down to 22nm Design Rule -- Eishi Ibe, Kenichi Shimbo, Hitoshi Taniguchi, Tadanobu Toba (Hitachi, Ltd.)  CPM2009-139 ICD2009-68 Link to ES Tech. Rep. Archives: CPM2009-139 ICD2009-68 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The status-of-the-art in failures and their mechanisms of CMOS memories and logic gates induced by terrestrial neutrons are reviewed. Soft-errors in SRAMs down to 22nm design rule are predicted by simulation and their impacts on logic gates and electronic systems are discussed. | |
| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | terrestrial neutron / CMOS / SRAM / soft-error / logic device / latch / electronic system / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 317, CPM2009-139, pp. 29-34, Dec. 2009. | |
| Paper # | CPM2009-139 | |
| Date of Issue | 2009-11-25 (CPM, ICD) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | CPM2009-139 ICD2009-68 Link to ES Tech. Rep. Archives: CPM2009-139 ICD2009-68 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2009-12-02 - 2009-12-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kochi City Culture-Plaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2009 ―New Field of VLSI Design― |
| Paper Information | |
| Registration To | CPM |
| Conference Code | 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | Failures due to Terrestriall Neutrons in Most Advanced Semicondutor Devices |
| Sub Title (in English) | Impacts and Hardening Techniques down to 22nm Design Rule |
| Keyword(1) | terrestrial neutron |
| Keyword(2) | CMOS |
| Keyword(3) | SRAM |
| Keyword(4) | soft-error |
| Keyword(5) | logic device |
| Keyword(6) | latch |
| Keyword(7) | electronic system |
| Keyword(8) | |
| 1st Author's Name | Eishi Ibe |
| 1st Author's Affiliation | Hitachi, Ltd. (Hitachi, Ltd.) |
| 2nd Author's Name | Kenichi Shimbo |
| 2nd Author's Affiliation | Hitachi, Ltd. (Hitachi, Ltd.) |
| 3rd Author's Name | Hitoshi Taniguchi |
| 3rd Author's Affiliation | Hitachi, Ltd. (Hitachi, Ltd.) |
| 4th Author's Name | Tadanobu Toba |
| 4th Author's Affiliation | Hitachi, Ltd. (Hitachi, Ltd.) |
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| Speaker | Author-1 |
| Date Time | 2009-12-02 13:50:00 |
| Presentation Time | 35 minutes |
| Registration for | CPM |
| Paper # | CPM2009-139, ICD2009-68 |
| Volume (vol) | vol.109 |
| Number (no) | no.317(CPM), no.318(ICD) |
| Page | pp.29-34 |
| #Pages | 6 |
| Date of Issue | 2009-11-25 (CPM, ICD) |
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