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Paper Abstract and Keywords
Presentation 2009-12-03 13:45
A Yield Model with Testability and Repairability
Yujiro Amano, Yuki Yoshikawa, Hideyuki Ichihara, Tomoo Inoue (Hiroshima City Univ.) VLD2009-54 DC2009-41
Abstract (in Japanese) (See Japanese page) 
(in English) For deep-submicron technology, the increase in transitive and permanent faults of LSIs is a critical problem due to the considerable loss of production
yield and the large increase in defect level\cite{itrs}. In this paper, we focus on repairable and testable designs of logic circuits, and propose a
new yield model, which represents the impacts of these designs on production yield and defect level. The proposed model is applied to three testable
designs and one repairable design to clarify the relationship between the designs and the production cost / reliability of LSIs.
Keyword (in Japanese) (See Japanese page) 
(in English) yield / defect level / design-for-testability / repairable design / / / /  
Reference Info. IEICE Tech. Rep., vol. 109, no. 316, DC2009-41, pp. 89-94, Dec. 2009.
Paper # DC2009-41 
Date of Issue 2009-11-25 (VLD, DC) 
ISSN Print edition: ISSN 0913-5685    Online edition: ISSN 2432-6380
Copyright
and
reproduction		 All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034)
Download PDF VLD2009-54 DC2009-41

Conference Information
Committee VLD DC IPSJ-SLDM CPSY RECONF ICD CPM  
Conference Date 2009-12-02 - 2009-12-04 
Place (in Japanese) (See Japanese page) 
Place (in English) Kochi City Culture-Plaza 
Topics (in Japanese) (See Japanese page) 
Topics (in English) Design Gaia 2009 ―New Field of VLSI Design― 
Paper Information
Registration To DC 
Conference Code 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM 
Language Japanese 
Title (in Japanese) (See Japanese page) 
Sub Title (in Japanese) (See Japanese page) 
Title (in English) A Yield Model with Testability and Repairability 
Sub Title (in English)  
Keyword(1) yield  
Keyword(2) defect level  
Keyword(3) design-for-testability  
Keyword(4) repairable design  
Keyword(5)  
Keyword(6)  
Keyword(7)  
Keyword(8)  
1st Author's Name Yujiro Amano  
1st Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
2nd Author's Name Yuki Yoshikawa  
2nd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
3rd Author's Name Hideyuki Ichihara  
3rd Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
4th Author's Name Tomoo Inoue  
4th Author's Affiliation Hiroshima City University (Hiroshima City Univ.)
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Speaker Author-1 
Date Time 2009-12-03 13:45:00 
Presentation Time 20 minutes 
Registration for DC 
Paper # VLD2009-54, DC2009-41 
Volume (vol) vol.109 
Number (no) no.315(VLD), no.316(DC) 
Page pp.89-94 
#Pages 6 
Date of Issue 2009-11-25 (VLD, DC) 

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