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| Presentation | 2009-12-03 13:25 A Case Study of Error Correction Technique for SRAM-based FPGA using the Partial Reconfiguration Noritaka Kai, Yoshiaki Tsutsumi, Motoki Amagasaki, Morihiro Kuga, Toshinori Sueyoshi (Kumamoto Univ.)  RECONF2009-41 |
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| Abstract | (in Japanese) | (See Japanese page) |
| (in English) | The present paper describes an error correction technique for SRAM-based Field Programmable Gate Arrays (FPGAs) using the partial reconfiguration, which can handle the effects of Single Event Upsets (SEUs). We propose the error correction method using Frame-based partial reconfiguration from the configuration data of the FPGA. Although the only frame which affected SEU is reconfigured by using this method, this mothod is not supported officially on Xilinx EDA tools. The present study shows validity of frame-based partial reconfiguration method about combinational circuits and sequential circuits. As a result, the errors in combinational circuits and sequential circuits are corrected by using frame-based partial reconfiguration. In the case of sequential circuit, flip-flop stored adjacent data when frame-based partial reconfiguration. |
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| Keyword | (in Japanese) | (See Japanese page) |
| (in English) | FPGA / partial reconfiguration / frame / error correction / SEU / / / | |
| Reference Info. | IEICE Tech. Rep., vol. 109, no. 320, RECONF2009-41, pp. 1-6, Dec. 2009. | |
| Paper # | RECONF2009-41 | |
| Date of Issue | 2009-11-26 (RECONF) | |
| ISSN | Print edition: ISSN 0913-5685 Online edition: ISSN 2432-6380 | |
| Copyright and reproduction |
All rights are reserved and no part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopy, recording, or any information storage and retrieval system, without permission in writing from the publisher. Notwithstanding, instructors are permitted to photocopy isolated articles for noncommercial classroom use without fee. (License No.: 10GA0019/12GB0052/13GB0056/17GB0034/18GB0034) | |
| Download PDF | RECONF2009-41 |
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| Conference Information | |
| Committee | VLD DC IPSJ-SLDM CPSY RECONF ICD CPM |
| Conference Date | 2009-12-02 - 2009-12-04 |
| Place (in Japanese) | (See Japanese page) |
| Place (in English) | Kochi City Culture-Plaza |
| Topics (in Japanese) | (See Japanese page) |
| Topics (in English) | Design Gaia 2009 ―New Field of VLSI Design― |
| Paper Information | |
| Registration To | RECONF |
| Conference Code | 2009-12-VLD-DC-SLDM-CPSY-RECONF-ICD-CPM |
| Language | Japanese |
| Title (in Japanese) | (See Japanese page) |
| Sub Title (in Japanese) | (See Japanese page) |
| Title (in English) | A Case Study of Error Correction Technique for SRAM-based FPGA using the Partial Reconfiguration |
| Sub Title (in English) | |
| Keyword(1) | FPGA |
| Keyword(2) | partial reconfiguration |
| Keyword(3) | frame |
| Keyword(4) | error correction |
| Keyword(5) | SEU |
| Keyword(6) | |
| Keyword(7) | |
| Keyword(8) | |
| 1st Author's Name | Noritaka Kai |
| 1st Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 2nd Author's Name | Yoshiaki Tsutsumi |
| 2nd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 3rd Author's Name | Motoki Amagasaki |
| 3rd Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 4th Author's Name | Morihiro Kuga |
| 4th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
| 5th Author's Name | Toshinori Sueyoshi |
| 5th Author's Affiliation | Kumamoto University (Kumamoto Univ.) |
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| Speaker | Author-1 |
| Date Time | 2009-12-03 13:25:00 |
| Presentation Time | 20 minutes |
| Registration for | RECONF |
| Paper # | RECONF2009-41 |
| Volume (vol) | vol.109 |
| Number (no) | no.320 |
| Page | pp.1-6 |
| #Pages | 6 |
| Date of Issue | 2009-11-26 (RECONF) |
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